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| document no. a13195ej5v1dm00 (5th edition) date published january 2002 ns cp(n) printed in japan 1998 ? design manual 78k/0 core v851 tm core v853 tm core v30mx tm V30MZ tm nb85e nb85e901 nb85et nb85e500 nu85e500 nu85e502 cb-9 family vx/vm type core library 0.35 m cmos cell-based ic (cbic) cpu core, memory controller
2 design manual a13195ej5v0dm [memo] 3 design manual a13195ej5v0dm opencad, v850 family, v851, v853, v30mx, V30MZ, v30hl, and v.sim are trademarks of nec corporation. verilog-xl is a trademark of cadence design systems, inc. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 4 design manual a13195ej5v0dm purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of november, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? 5 design manual a13195ej5v0dm regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v?lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci?n en espa?a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60 6 design manual a13195ej5v0dm major revisions in this edition pages description p.17 addition of 1.3 timing verification p.91 addition of 5.3.7 timing verification p.105 addition of 6.2.2 timing verification p.108 modification of 6.5.2 recommended operation range p.134 modification of 7.4.4 (3) vsb arbitration timing p.144 modification of 7.4.4 (8) vfb access timing p.175 modification of 9.4.2 recommended operation range p.176 modification of 9.4.4 (1) clock timing p.177 modification of 9.4.4 (3) vsb arbitration timing p.186 modification of 9.4.4 (8) vfb access timing p.262 modification of 12.4.4 (1) sdram read timing p.264 modification of 12.4.4 (2) sdram write timing p.267 modification of 12.4.4 (4) vsb timing pp.268 to 270 addition of appendix revision history the mark shows major revised points. 7 design manual a13195ej5v0dm introduction readers this manual is intended for users who will design asic employing the cb-9 family vx/vm type of nec?s high-speed, highly integrated cmos cbic. purpose the purpose of this manual is to help the user understand the outlines and electrical specifications of the following cpu cores, run control unit (rcu), and memory controllers (memc) necessary for designing the system. 8 design manual a13195ej5v0dm related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? cb-9 family vx/vm type design manual (a12745e) ? cb-9 family vx/vm type design manual 78k/0 core user?s manual (a13688e) ? cb-9 family vx/vm type v851 core, v853 core design manual user?s manual (a13602e) ? cb-9 family vx/vm type nb85e, nb85et design manual (a14335e) ? 78k/0 core user?s manual (a13142e) ? v851 core hardware user?s manual (a12757e) ? v853 core hardware user?s manual (a13141e) ? v30mx hardware user?s manual (a11897e) ? V30MZ hardware user?s manual (a13761e) ? nb85e hardware user?s manual (a13971e) ? nb85et hardware user?s manual (a14342e) ? memory controller nb85e, nb85et user?s manual (a14206e) the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 9 design manual a13195ej5v0dm contents chapter 1 common part .................................................................................................................... 14 1. 1 macro area............................................................................................................... .....................14 1. 2 test design.............................................................................................................. .....................15 1. 2. 1 test pattern .......................................................................................................... .............................15 1. 2. 2 test program for total chip simulation................................................................................ ...............16 1. 2. 3 test pins ............................................................................................................. ..............................16 1. 2. 4 initialize ............................................................................................................ .................................17 1. 2. 5 prohibition on spike input............................................................................................ ......................17 1. 3 timing verification...................................................................................................... .................17 chapter 2 78k/0 core.......................................................................................................... .................18 2. 1 outline................................................................................................................... ........................18 2. 1. 1 symbol diagram ........................................................................................................ ........................19 2. 1. 2 pin capacitance....................................................................................................... ..........................21 2. 2 pin functions ............................................................................................................ ...................24 2. 3 electrical specifications................................................................................................ ..............26 2. 3. 1 absolute maximum ratings.............................................................................................. ..................26 2. 3. 2 recommended operation range ........................................................................................... ............26 2. 3. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) .............................................................26 2. 3. 4 ac characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v, load capacitance of output pin c l = 5 pf)..........................................................................................26 2. 3. 5 low-voltage data retention characteristics of data memory in stop mode (t a = ? 40 to +85c) .....32 2. 4 timing chart ............................................................................................................. ....................32 chapter 3 v851 core........................................................................................................... .................42 3. 1 outline.................................................................................................................. .........................42 3. 1. 1 symbol diagram ........................................................................................................ ........................43 3. 1. 2 pin capacitance....................................................................................................... ..........................45 3. 2 resetb signal............................................................................................................ .................47 3. 3 initialization of internal registers..................................................................................... ..........47 3. 4 pin functions ............................................................................................................ ...................48 3. 5 electrical specifications................................................................................................ ..............50 3. 5. 1 absolute maximum ratings.............................................................................................. ..................50 3. 5. 2 recommended operation range ........................................................................................... ............50 3. 5. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) .............................................................50 3. 5. 4 ac characteristics (t a = ? 40 to +85c, v dd = 3.3 v 0.3 v) .............................................................52 chapter 4 v853 core........................................................................................................... .................62 4. 1 outline.................................................................................................................. .........................62 4. 1. 1 symbol diagram ........................................................................................................ ........................63 4. 1. 2 pin capacitance....................................................................................................... ..........................65 4. 2 resetb signal............................................................................................................ .................68 4. 3 initialization of internal registers..................................................................................... ..........68 4. 4 pin functions ............................................................................................................ ...................69 4. 5 electrical specifications................................................................................................ ..............71 4. 5. 1 absolute maximum ratings.............................................................................................. ..................71 10 design manual a13195ej5v0dm 4. 5. 2 recommended operation range........................................................................................... ............ 71 4. 5. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ............................................................ 71 4. 5. 4 ac characteristics (t a = ? 40 to +85c, v dd = 3.3 v 0.3 v) ............................................................ 73 chapter 5 v30mx ............................................................................................................... .................... 86 5. 1 outline .................................................................................................................. ........................ 86 5. 1. 1 symbol diagram ........................................................................................................ ....................... 87 5. 1. 2 pin capacitance....................................................................................................... ......................... 88 5. 2 notes for initialization................................................................................................. ................ 89 5. 3 notes for pattern generation and circuit designing ............................................................... 90 5. 3. 1 handling 3-state outputs .............................................................................................. .................... 90 5. 3. 2 reset signal .......................................................................................................... ......................... 90 5. 3. 3 clk input............................................................................................................. ............................. 90 5. 3. 4 initialization of internal registers.................................................................................. ..................... 91 5. 3. 5 restriction of test program size...................................................................................... .................. 91 5. 3. 6 segment specification in the test program ............................................................................. .......... 91 5. 3. 7 timing verification ................................................................................................... ......................... 91 5. 4 pin functions............................................................................................................ ................... 92 5. 5 electrical specifications ................................................................................................ ............. 93 5. 5. 1 absolute maximum ratings .............................................................................................. ................. 93 5. 5. 2 recommended operation range........................................................................................... ............ 93 5. 5. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ............................................................ 93 5. 5. 4 ac characteristics (t a = ? 40 to +85c, v dd = 3.3 v 0.3 v) ............................................................ 94 chapter 6 V30MZ ............................................................................................................... .................. 103 6. 1 outline .................................................................................................................. ...................... 103 6. 1. 1 symbol diagram ........................................................................................................ ..................... 104 6. 1. 2 pin capacitance....................................................................................................... ....................... 104 6. 2 notes for simulation execution ........................................................................................... .... 105 6. 2. 1 notes for v.sim simulation ............................................................................................ ................. 105 6. 2. 2 timing verification................................................................................................... ....................... 105 6. 3 notes for initialization................................................................................................. .............. 106 6. 3. 1 reset signal .......................................................................................................... ....................... 106 6. 3. 2 clk input............................................................................................................. ........................... 106 6. 3. 3 initialization of internal registers.................................................................................. ................... 106 6. 4 pin functions............................................................................................................ ................. 107 6. 5 electrical specifications (preliminary) .................................................................................. .. 108 6. 5. 1 absolute maximum ratings .............................................................................................. ............... 108 6. 5. 2 recommended operation range........................................................................................... .......... 108 6. 5. 3 dc characteristics (t a = ? 40 to +85 c).......................................................................................... 108 6. 5. 4 ac characteristics (t a = ? 40 to +85c) .......................................................................................... 109 chapter 7 nb85e ............................................................................................................... .................. 114 7. 1 outline .................................................................................................................. ...................... 114 7. 1. 1 symbol diagram ........................................................................................................ ..................... 115 7. 1. 2 pin capacitance....................................................................................................... ....................... 117 7. 2 initialization of internal registers..................................................................................... ....... 127 7. 3 pin functions............................................................................................................ ................. 128 11 design manual a13195ej5v0dm 7. 4 electrical specifications (preliminary) .................................................................................. ...132 7. 4. 1 absolute maximum ratings.............................................................................................. ................132 7. 4. 2 recommended operation range ........................................................................................... ..........132 7. 4. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ...........................................................132 7. 4. 4 ac characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ...........................................................133 chapter 8 nb85e901 ............................................................................................................ ................151 8. 1 outline.................................................................................................................. .......................151 8. 1. 1 symbol diagram ........................................................................................................ ......................151 8. 1. 2 pin capacitance....................................................................................................... ........................152 8. 2 pin functions ............................................................................................................ .................154 8. 3 electrical specifications (preliminary) .................................................................................. ...155 8. 3. 1 absolute maximum ratings.............................................................................................. ................155 8. 3. 2 recommended operation range ........................................................................................... ..........155 8. 3. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ...........................................................155 8. 3. 4 ac characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ...........................................................155 chapter 9 nb85et .............................................................................................................. ..................156 9. 1 outline.................................................................................................................. .......................156 9. 1. 1 symbol diagram ........................................................................................................ ......................157 9. 1. 2 pin capacitance....................................................................................................... ........................159 9. 2 initialization of internal registers..................................................................................... ........169 9. 3 pin functions ............................................................................................................ .................170 9. 4 electrical specifications (preliminary) .................................................................................. ...175 9. 4. 1 absolute maximum ratings.............................................................................................. ................175 9. 4. 2 recommended operation range ........................................................................................... ..........175 9. 4. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ...........................................................175 9. 4. 4 ac characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ...........................................................176 chapter 10 nb85e500 ........................................................................................................... ...............194 10. 1 outline................................................................................................................. ........................194 10. 1. 1 symbol diagram ....................................................................................................... .....................194 10. 1. 2 pin capacitance...................................................................................................... .......................196 10. 2 initialization of internal registers.................................................................................... .........201 10. 3 pin functions ........................................................................................................... ..................202 10. 4 electrical specifications (preliminary) ................................................................................. ....205 10. 4. 1 absolute maximum ratings............................................................................................. ...............205 10. 4. 2 recommended operation range .......................................................................................... .........205 10. 4. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) .........................................................205 10. 4. 4 ac characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) .........................................................206 chapter 11 nu85e500 ........................................................................................................... ...............224 11. 1 outline................................................................................................................. ........................224 11. 1. 1 symbol diagram ...................................................................................................... .....................224 11. 1. 2 pin capacitance..................................................................................................... .......................226 11. 2 initialization of internal registers.................................................................................... .........231 11. 3 pin functions ........................................................................................................... ..................232 11. 4 electrical specifications (preliminary) ................................................................................. ....235 12 design manual a13195ej5v0dm 11. 4. 1 absolute maximum ratings ............................................................................................. .............. 235 11. 4. 2 recommended operation range.......................................................................................... ......... 235 11. 4. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ........................................................ 235 11. 4. 4 ac characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ........................................................ 236 chapter 12 nu85e502 ........................................................................................................... .............. 254 12. 1 outline ................................................................................................................. ....................... 254 12. 1. 1 symbol diagram ....................................................................................................... .................... 255 12. 1. 2 pin capacitance...................................................................................................... ...................... 256 12. 2 initialization of internal registers.................................................................................... ........ 258 12. 3 pin functions........................................................................................................... .................. 259 12. 4 electrical specifications (preliminary) ................................................................................. ... 260 12. 4. 1 absolute maximum ratings ............................................................................................. .............. 260 12. 4. 2 recommended operation range.......................................................................................... ......... 260 12. 4. 3 dc characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ........................................................ 260 12. 4. 4 ac characteristics (t a = ? 40 to +85 c, v dd = 3.3 v 0.3 v) ........................................................ 262 appendix revision history.................................................................................................... ........ 268 13 design manual a13195ej5v0dm list of figures figure no . title page 2-1 example of circuit construction of serial interface (iic0) input/output pin ...............................................32 3-1 resetb signal input example................................................................................................. ..................47 4-1 resetb signal input example................................................................................................. ..................68 5-1 reset signal input example .................................................................................................. ...................90 6-1 reset signal input example .................................................................................................. .................106 14 desi g n manual a13195ej5v0dm chapter 1 common part 1. 1 macro area the area of a macro is expressed as a number of grids. the number of grids is an index that indicates the area of the circuit of a cell-based ic. number of grids = x grids (size in x direction) y grids (size in y direction) for example, the circuit shown below consists of 35 grids. 1 8 15 22 29 2 9 16 23 30 3 10 17 24 31 4 11 18 25 32 5 12 19 26 33 6 13 20 27 34 7 14 21 28 35 x grids = 7 y grids = 5 chapter 1 common part 15 design manual a13195ej5v0dm 1. 2 test design test design is very important when designing the circuit of an asic. this section explains the test functions of a cpu core. these test functions are necessary when designing the cb-9 family vx/vm type using any of the cpu cores explained in this manual. 1. 2. 1 test pattern when developing a cb-9 family vx/vm type product including a cpu core, simulation is implemented for each internal block in the following three stages, unlike when the circuit consists of only user logic. (1) user logic separation simulation checks the functions of the user logic in detail. (2) test circuit check simulation checks the path (test bus) that tests the internal functions of the cpu core. the test patterns for the internal functions of the cpu cores have been created by nec. (3) total chip simulation checks mutual connection between the cpu core, user logic, and interface block. theoretically, it is possible to check the circuit operation in (1) through (3) with one test pattern, but it is more efficient to use the above three stages for the following reasons: (a) to avoid creating test pattern for checking cpu core functions in detail the internal circuits of the cpu core are very complicated and in effect a kind of black box. therefore, it is extremely difficult to create a simulation test pattern that can check the internal functions taking delicate timing into consideration, and it is practically impossible for the user to create a test pattern that tests all the internal functions of the cpu core. for this reason, separate the simulation process to check the internal circuits of the cpu core from the user logic block, and insert a test circuit. nec offers ready-made test patterns. (b) to mitigate the simulation load of the cpu core, and to avoid the limitations of using a cad tool that can simulate the cpu core some cpu cores have several 10,000 of gates and therefore have a heavy simulation load. consequently, the types of machines that can execute simulation of these cpu cores are limited and the execution time is very long. the user logic separation simulation in (1) above can mitigate the simulation load of the user logic block where a mistake is most likely to occur, by creating a model, called a dummy macro, of only the cpu core cut-out section. consequently, the design period can be shortened. in addition, a wider range of cad tools can be used. note, however, that the kinds of tools that can use a dummy macro are also limited. chapter 1 common part 16 design manual a13195ej5v0dm 1. 2. 2 test program for total chip simulation a test program that is executed by the cpu core is also necessary for executing total chip simulation. when using an external memory instead of the internal memory of the cb-9 family vx/vm type, simulation is easier if a circuit in which an external memory is connected to the circuit of the cb-9 family vx/vm type is created and if total chip simulation is executed in the same manner as above, rather than if instructions are given in the form of a test pattern. in this case, the test pattern for the actual chip can be created if the signals at the cut-out section of the circuit block of the original cb-9 family vx/vm type is dumped. for details, refer to design manual of each cpu core. 1. 2. 3 test pins (1) tbo (n:0), tbi (m:0) these are test pins for simulation to check the test circuit. the pins of a cpu core can be broadly divided into test pins and normal pins used for application circuit design. the signals input to or output from the test pins are separated from those input to or output from the normal pins. the number of test pins differs depending on the cpu core. (2) bunri, test these pins select the modes of the test pins and normal pins. depending on the combination of the signals input to these pins, the cpu core operates as follows: bunri test operation mode 0 0 normal mode 1 1 0 test mode (standby test) 1 test mode (unit test) (a) normal mode this mode is used to perform normal operations such as during total chip simulation. in this mode, the normal pins are valid. (b) test mode (standby test) this mode is used when the cpu core is not tested during test circuit check simulation or user logic separation simulation. (c) test mode (unit test) this mode is used when the cpu core is tested during test circuit check simulation. each pin is in the following status in each operation mode. chapter 1 common part 17 design manual a13195ej5v0dm mode normal pins test pins input output 3-state output bidirectional input (tbix) output (tbox) normal mode valid valid valid valid input ignored test mode (standby test) input ignored undefined high impedance input ignored high impedance test mode (unit test) valid valid for details on circuit design, refer to cb-9 family vx/vm type design manual (a12745e) . 1. 2. 4 initialize the steps for initialization are explained in below. initialize each cpu core by following these steps. (1) input an initialization pattern from the normal pins (a) apply a reset pulse apply a pulse with a specified width or more. some cpus require operation of the clock signal while the reset pulse is input. (b) write initial values to the internal registers some registers, such as the stack pointer of the cpu, require that initial values be set in advance. (2) input an initialization pattern from a test pin this step is used to initialize a cpu core for which nec has already created an initialization pattern because the test pattern is very complicated. in this case, the initialization pattern is input in the same test mode as for test circuit check simulation, and then the mode is changed back to that of total chip simulation. although this step allows you to ignore the details of the pattern, it requires care when changing the mode from test to normal, so that a malfunction does not occur. 1. 2. 5 prohibition on spike input it is necessary to take care not to input a spike to input pins that operate at the edge of an input signal, such as interrupt and clock input pins. 1. 3 timing verification verify that the input timing is satisfied at the boundary between the cpu core and memory controller using a delay analysis tool. observe the description on timing verification for each cpu core and memory controller if described in this manual (refer to the design manual of each cpu core). 18 design manual a13195ej5v0dm chapter 2 78k/0 core the 78k/0 core is a cpu core containing many peripheral functions such as timers, serial interfaces, and an interrupt controller. the instruction set of the 78k/0 core is common to that of the 78k/0 series 8-bit single-chip microcontrollers. 2. 1 outline ? cpu function: 78k/0 series standard ? minimum instruction execution time: 0.24 s (maximum input frequency: 8.38 mhz) ? internal memory part number rom capacity ram capacity nak0hm0 0 (romless) 1 kb nak0hm4 32 kb (mask rom) nak0hm8 60 kb (mask rom) ? port up to 128 port pins can be used by using an i/o buffer. input port: 64 pins output port: 64 pins ? timers/counters 16-bit timer/event counter: 1 ch 8-bit timer/event counter: 2 chs watch timer: 1 ch watchdog timer: 1 ch ? serial interface 3-wire serial i/o mode: 2 chs uart mode: 2 chs i 2 c bus mode: 2 chs ? vectored interrupt source: 29 (internal : 17, external : 12) ? external memory expansion space: 64 kb (address/din/dout separation) ? standby function: halt/stop mode (can be released by interrupt) ? supply voltage: v dd = 3.0 to 3.6 v chapter 2 78k/0 core 19 design manual a13195ej5v0dm 2. 1. 1 symbol diagram (1) nak0hm0 number of grids 147k grids 192k grids (value including wiring area) number of separation simulation patterns 165k a(15:0) scli00 sdao00 txd31 rxd31 rxd30 in pin(7:0) out pon(7:0) in int(11:0) in out in in out in in out in out in out si30 so30 si31 sck31ib sck31ob sdai00 sclo00 out din(7:0) in dout(7:0) astb out rdb out wrb out x1in in stopx1 out xt1in in stopxt1 out romless in resetb in tbi (23:0) tbo (38:0) test bunri in in out in out waitb in in sck30ib out sck30ob out so31 txd30 out scli01 sdao01 in out in out sdai01 sclo01 in ti00 in ti01 out to0 in ti50 out to50 in ti51 out to51 out ckupcl out ckubuz totalcm in dmbtm in emumd in [n = 7-0] intflt in flashen in chapter 2 78k/0 core 20 design manual a13195ej5v0dm (2) nak0hm4, nak0hm8 number of grids number of separation simulation patterns ? nak0hm4 : 193k grids ? nak0hm4: 230k 243k grids (value including wiring area) ? nak0hm8: 285k ? nak0hm8 : 217k grids 270k grids (value including wiring area) a(15:0) scli00 sdao00 txd31 rxd31 rxd30 in pin(7:0) out pon(7:0) in int(11:0) in out in in out in in out in out in out si30 so30 si31 sck31ib sck31ob sdai00 sclo00 out din(7:0) in dout(7:0) astb out rdb out wrb out x1in in stopx1 out xt1in in stopxt1 out romless in resetb in tbi (23:0) tbo (38:0) test bunri in in out in out waitb in in sck30ib out sck30ob out so31 txd30 out scli01 sdao01 in out in out sdai01 sclo01 in ti00 in ti01 out to0 in ti50 out to50 in ti51 out to51 out ckupcl out ckubuz totalcm in dmbtm in emumd in [n = 7-0] chapter 2 78k/0 core 21 design manual a13195ej5v0dm 2. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) nak0hm0 (a) input pins pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) din7 to din0 0.102 2.002 scli00 0.233 2.133 waitb 0.059 1.959 sdai01 0.067 1.967 x1in 0.059 1.959 scli01 0.065 1.965 xt1in 0.046 1.946 ti00 0.056 1.956 romless 0.630 2.530 ti01 0.075 1.975 resetb 0.109 2.009 ti50 0.045 1.945 pin7 to pin0 (n = 7 to 0) 0.153 2.053 ti51 0.050 1.950 int11 to int0 0.210 2.110 tbi23 to tbi0 1.019 2.919 si30 0.062 1.962 test 3.983 5.883 sck30ib 0.068 1.968 bunri 4.455 6.355 si31 0.081 1.981 totalcm 1.544 3.444 sck31ib 0.168 2.068 dmbtm 0.859 2.759 rxd30 0.087 1.987 emumd 0.747 2.647 rxd31 0.152 2.052 intflt 0.373 2.273 sdai00 0.082 1.982 flashen 0.629 2.529 (b) output pins pin name c max (pf) pin name c max (pf) pin name c max (pf) a15 to a0 6.459 so30 6.561 sdao01 6.567 dout7 to dout0 6.501 sck30ob 6.561 sclo01 6.562 astb 6.452 so31 6.545 to0 6.566 rdb 6.415 sck31ob 6.523 to50 6.567 wrb 6.500 txd30 6.555 to51 6.566 stopx1 6.564 txd31 6.522 ckupcl 6.550 stopxt1 6.555 sdao00 6.496 ckubuz 6.545 pon7 to pon0 (n = 7 to 0) 6.496 sclo00 6.527 tbo38 to tbo0 6.322 chapter 2 78k/0 core 22 design manual a13195ej5v0dm (2) nak0hm4 (a) input pins pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) din7 to din0 0.090 1.990 sdai00 0.057 1.957 waitb 0.061 1.961 scli00 0.042 1.942 x1in 0.049 1.949 sdai01 0.043 1.943 xt1in 0.045 1.945 scli01 0.046 1.946 romless 0.569 2.469 ti00 0.056 1.956 resetb 0.047 1.947 ti01 0.073 1.973 pin7 to pin0 (n = 7 to 0) 0.178 2.078 ti50 0.081 1.981 int11 to int0 0.258 2.158 ti51 0.050 1.950 si30 0.049 1.949 tbi23 to tbi0 0.925 2.825 sck30ib 0.043 1.943 test 4.125 6.025 si31 0.084 1.984 bunri 4.493 6.393 sck31ib 0.068 1.968 totalcm 1.434 3.334 rxd30 0.058 1.958 dmbtm 0.794 2.694 rxd31 0.064 1.964 emumd 0.779 2.679 (b) output pins pin name c max (pf) pin name c max (pf) pin name c max (pf) a15 to a0 6.445 so30 6.568 sdao01 6.568 dout7 to dout0 6.542 sck30ob 6.568 sclo01 6.567 astb 6.529 so31 6.563 to0 6.554 rdb 6.564 sck31ob 6.559 to50 6.528 wrb 6.562 txd30 6.557 to51 6.568 stopx1 6.557 txd31 6.566 ckupcl 6.528 stopxt1 6.540 sdao00 6.530 ckubuz 6.561 pon7 to pon0 (n = 7 to 0) 6.347 sclo00 6.564 tbo38 to tbo0 6.322 chapter 2 78k/0 core 23 design manual a13195ej5v0dm (3) nak0hm8 (a) input pins pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) din7 to din0 0.090 1.990 sdai00 0.057 1.957 waitb 0.061 1.961 scli00 0.042 1.942 x1in 0.049 1.949 sdai01 0.043 1.943 xt1in 0.045 1.945 scli01 0.046 1.946 romless 0.569 2.469 ti00 0.056 1.956 resetb 0.047 1.947 ti01 0.073 1.973 pin7 to pin0 (n = 7 to 0) 0.178 2.078 ti50 0.081 1.981 int11 to int0 0.258 2.158 ti51 0.051 1.951 si30 0.049 1.949 tbi23 to tbi0 0.925 2.825 sck30ib 0.043 1.943 test 4.123 6.023 si31 0.084 1.984 bunri 4.493 6.393 sck31ib 0.068 1.968 totalcm 1.434 3.334 rxd30 0.058 1.958 dmbtm 0.794 2.694 rxd31 0.064 1.964 emumd 0.779 2.679 (b) output pins pin name c max (pf) pin name c max (pf) pin name c max (pf) a15 to a0 6.445 so30 6.568 sdao01 6.567 dout7 to dout0 6.542 sck30ob 6.568 sclo01 6.567 astb 6.529 so31 6.563 to0 6.554 rdb 6.564 sck31ob 6.559 to50 6.528 wrb 6.562 txd30 6.557 to51 6.568 stopx1 6.557 txd31 6.566 ckupcl 6.528 stopxt1 6.540 sdao00 6.530 ckubuz 6.561 pon7 to pon0 (n = 7 to 0) 6.347 sclo00 6.564 tbo38 to tbo0 6.322 chapter 2 78k/0 core 24 design manual a13195ej5v0dm 2. 2 pin functions (1/2) pin name i/o function a15 to a0 output output address output for external access. din7 to din0 input input data input for external access. dout7 to dout0 output output data output for external access. astb output external address strobe signal. rdb output external read strobe signal. wrb output external write strobe signal. waitb input control signal input to insert wait to external bus cycle. x1in input main system clock oscillator input. stopx1 output main system clock oscillator stop signal. xt1in input subsystem clock oscillator input. stopxt1 output subsystem clock oscillator stop signal. romless input romless mode select signal. resetb input system reset input. pin7 to pin0 (n = 7 to 0) input 8-bit input port. pon7 to pon0 (n = 7 to 0) output 8-bit output port. int11 to int0 input external interrupt request input. si30 input serial interface (sio30) serial data input. so30 output serial interface (sio30) serial data output. sck30ib input serial interface (sio30) serial clock input. sck30ob output serial interface (sio30) serial clock output. si31 input serial interface (sio31) serial data input. so31 output serial interface (sio31) serial data output. sck31ib input serial interface (sio31) serial clock input. sck31ob output serial interface (sio31) serial clock output. rxd30 input asynchronous serial interface (uart30) serial data input. txd30 output asynchronous serial interface (uart30) serial data output. rxd31 input asynchronous serial interface (uart31) serial data input. txd31 output asynchronous serial interface (uart31) serial data output. sdai00 input serial interface (iic00) serial data input. sdao00 output serial interface (iic00) serial data output. scli00 input serial interface (iic00) serial clock input. sclo00 output serial interface (iic00) serial clock output. sdai01 input serial interface (iic01) serial data input. sdao01 output serial interface (iic01) serial data output. scli01 input serial interface (iic01) serial clock input. sclo01 output serial interface (iic01) serial clock output. ti00 input capture trigger input 1 to capture register of 16-bit timer (tm0). ti01 input capture trigger input 2 to capture register of 16-bit timer (tm0). chapter 2 78k/0 core 25 design manual a13195ej5v0dm (2/2) pin name i/o function to0 output 16-bit timer (tm0) pwm output. ti50 input external count clock input to 8-bit timer (tm50). to50 output 8-bit timer (tm50) output. ti51 input external count clock input to 8-bit timer (tm51). to51 output 8-bit timer (tm51) output. ckupcl output clock output. ckubuz output buzzer output. tbi23 to tbi0 input test bus input signal. tbo38 to tbo0 output test bus output signal. test input test bus control signal input. bunri input normal test mode select signal input. totalcm input test mode select signal input. dmbtm input test mode select signal input. emumd input emulation mode. chapter 2 78k/0 core 26 design manual a13195ej5v0dm 2. 3 electrical specifications the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 2. 3. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 2. 3. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c 2. 3. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode 0.8 1.2 ma/mhz i dd2 in halt mode 0.2 0.3 ma/mhz supply current i dd3 in stop mode 1.0 10 a 2. 3. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v, load capacitance of output pin c l = 5 pf) (1) clock timing parameter symbol conditions min. max. unit clkin cycle time <1> t cyx 120 ns clkin input high-level width note <2> t wxh 50 64 ns clkin input low-level width note <3> t wxl 50 64 ns cpu operating frequency ? 08.38mhz note the slew rate clock is taken into consideration for the high-level and low-level widths of the clock, where the rate of change in the duty factor is 15% max. chapter 2 78k/0 core 27 design manual a13195ej5v0dm (2) fetch operation parameter symbol conditions min. max. unit when divider is not used, clkin 25 ns delay time from clkin to address <4> t dxa when divider is used, clkin 25 ns delay time from clkin to astb <5> t dxst 25 ns delay time from clkin to rdb <6> t dxr 25 ns when divider is not used, clkin 15 ns address hold time from clkin <7> t hxa when divider is used, clkin 15 ns when divider is not used, clkin 0.5t cyx ? 20 ns 40 ns setup time from clkin to waitb <8> t sxwt when divider is used, clkin 0.5t cyx ? 20 ns 40 ns when divider is not used, clkin 25 ns hold time from clkin to waitb <9> t hxwt when divider is used, clkin 25 ns when divider is not used, clkin 0.5t cyx ? 25 ns 35 ns delay time from clkin to waitb <10> t dxwt when divider is used, clkin 0.5t cyx ? 25 ns 35 ns delay time from address to astb <15> t dast 0.5t cyk ? 30 ns 30 ns astb high-level width <16> t wsth 0.5t cyk ? 10 ns 50 ns setup time from address to data input* <17> t said (1.5 + n)t cyk ? 50 ns 130 ns setup time from rdb to data input* <18> t srid (1.0 + n)t cyk ? 50 ns 70 ns rdb low-level width* <19> t wrl (1.0 + n)t cyk ? 15 ns 105 ns read data hold time <20> t hrid 0ns delay time from rdb to astb * <21> t drstl 0.5t cyk ? 20 ns 40 ns address hold time (from rdb )* <22> t hra 0.5t cyk ? 20 ns 40 ns delay time from rdb to astb * <23> t drsth t cyk ? 20 ns 100 ns setup time from astb to data input* <24> t sstid (1.0 + n)t cyk ? 50 ns 70 ns setup time from address to waitb * <31> t sawt t cyk ? 40 ns 80 ns setup time from astb to waitb * <32> t sstwt 0.5t cyk ? 30 ns 30 ns hold time from astb to waitb * <33> t hstwt (n ? 0.5)t cyk + 10 ns 70 ns delay time from astb to waitb * <34> t dstwt (0.5 + n)t cyk ? 40 ns 140 ns setup time from rdb to waitb * <35> t srwt 0.5t cyk ? 30 ns 30 ns hold time from rdb to waitb * <36> t hrwt (n ? 0.5)t cyk + 10 ns 70 ns setup time from waitb to data input <38> t swtid 0.5t cyk ? 10 ns 50 ns delay time from waitb to rdb <39> t dwtr 0.5t cyk + 40 ns 100 ns remarks 1. t cyx : clkin cycle time (120 ns (min.)) remarks 2. t cyk : cpu clock selected with processor clock control register (pcc) (120 ns (min.)) remarks 3. n: number of wait cycles (software wait: n = 1, external wait input: n 1) remarks 4. the minimum and maximum values are calculated where t cyx = t cyk = 120 ns. remarks 5. the values of the operations marked * differ from the calculated value during data access read. chapter 2 78k/0 core 28 design manual a13195ej5v0dm (3) data access read operation parameter symbol conditions min. max. unit when divider is not used, clkin 25 ns delay time from clkin to address <4> t dxa when divider is used, clkin 25 ns delay time from clkin to astb <5> t dxst 25 ns delay time from clkin to rdb <6> t dxr 25 ns when divider is not used, clkin 15 ns hold time from clkin to address <7> t hxa when divider is used, clkin 15 ns setup time from clkin to waitb input <8> t sxwt 0.5t cyx ? 20 ns 40 ns hold time from clkin to waitb <9> t hxwt 25 ns when divider is not used, clkin 0.5t cyx ? 25 ns 35 ns delay time from clkin to waitb <10> t dxwt when divider is used, clkin 0.5t cyx ? 25 ns 35 ns delay time from address to astb <15> t dast 0.5t cyk ? 30 ns 30 ns astb high-level width <16> t wsth 0.5t cyk ? 10 ns 50 ns setup time from address to data input* <17> t said (2 + n)t cyk ? 50 ns 190 ns setup time from rdb to data input* <18> t srid (1.5 + n)t cyk ? 50 ns 130 ns rdb low-level width* <19> t wrl (1.5 + n)t cyk ? 15 ns 165 ns read data hold time <20> t hrid 0ns delay time from rdb to astb * <21> t drstl t cyk ? 20 ns 100 ns address hold time (from rdb )* <22> t hra t cyk ? 20 ns 100 ns delay time from rdb to astb * <23> t drsth 1.5t cyk ? 20 ns 160 ns setup time from astb to data input* <24> t sstid (1.5 + n)t cyk ? 50 ns 0 ns setup time from address to waitb * <31> t sawt 1.5t cyk ? 40 ns 140 ns setup time from astb to waitb * <32> t sstwt t cyk ? 30 ns 90 ns hold time from astb to waitb * <33> t hstwt nt cyk + 10 ns 130 ns delay time from astb to waitb * <34> t dstwt (1 + n)t cyk ? 40 ns 200 ns setup time from rdb to waitb * <35> t srwt t cyk ? 30 ns 90 ns hold time from rdb to waitb * <36> t hrwt nt cyk + 10 ns 130 ns delay time from rdb to waitb <37> t daswt (1 + n)t cyk ? 40 ns 200 ns setup time from waitb to data input <38> t swtid 0.5t cyk ? 10 ns 50 ns delay time from waitb to rdb <39> t dwtr 0.5t cyk + 40 ns 100 ns remarks 1. t cyx : clkin cycle time (120 ns (min.)) remarks 2. t cyk : cpu clock selected with processor clock control register (pcc) (120 ns (min.)) remarks 3. n: number of wait cycles (software wait: n = 1, external wait input: n 1) remarks 4. the minimum and maximum values are calculated where t cyx = t cyk = 120 ns. remarks 5. the values of the operations marked * differ from the calculated value during fetch. chapter 2 78k/0 core 29 design manual a13195ej5v0dm (4) data access write operation parameter symbol conditions min. max. unit when divider is not used, clkin 25 ns delay time from clkin to address <4> t dxa when divider is used, clkin 25 ns delay time from clkin to astb <5> t dxst 25 ns when divider is not used, clkin 15 ns hold time from clkin to address <7> t hxa when divider is used, clkin 15 ns when divider is not used, clkin 0.5 t cyx ? 20 ns 40 ns setup time from clkin to waitb <8> t sxwt when divider is used, clkin 0.5t cyx ? 20 ns 40 ns when divider is not used, clkin 25 ns hold time from clkin to waitb <9> t hxwt when divider is used, clkin 25 ns when divider is not used, clkin 0.5t cyx ? 25 ns 35 ns delay time from clkin to waitb <10> t dxwt when divider is used, clkin 0.5t cyx ? 25 ns 35 ns delay time from clkin to wrb <11> t dxw 25 ns delay time from clkin to data output <12> t dkod 75 ns write data hold time (from clkin) <13> t hkod 15 ns delay time from wrb to astb <14> t dwst t cyk ? 20 ns 100 ns delay time from address to astb <15> t dast 0.5t cyk ? 30 ns 30 ns astb high-level width <16> t wsth 0.5t cyk ? 10 ns 50 ns delay time from astb to wrb <25> t dstw t cyk ? 15 ns 105 ns wrb low-level width <26> t wwl (1.0 + n)t cyk ? 15 ns 105 ns delay time from wrb to data output <27> t dwod 50 ns data setup time (to wrb ) <28> t sodw (1.0 + n)t cyk ? 50 ns 70 ns data hold time (from wrb ) <29> t hodw 0.5t cyk ? 15 ns 45 ns address hold time (from wrb ) <30> t haw 0.5t cyk ? 20 ns 40 ns setup time from address to waitb <31> t sawt 2t cyk ? 40 ns 200 ns setup time from astb to waitb <32> t sstwt 1.5t cyk ? 30 ns 150 ns hold time from astb to waitb <33> t hstwt (0.5 + n)t cyk + 10 ns 190 ns delay time from astb to waitb <34> t dstwt (1.5 + n)t cyk ? 40 ns 260 ns delay time from waitb to wrb <40> t dwtw 0.5t cyk + 40 ns 100 ns setup time from wrb to waitb <41> t swwt 0.5t cyk ? 30 ns 30 ns hold time from wrb to waitb <42> t hwwt (n ? 0.5)t cyk + 10 ns 70 ns delay time from wrb to waitb <43> t dwwt (0.5 + n)t cyk ? 40 ns 140 ns remarks 1. t cyx : clkin cycle time (120 ns (min.)) remarks 2. t cyk : cpu clock selected with processor clock control register (pcc) (120 ns (min.)) remarks 3. n: number of wait cycles (software wait: n = 1, external wait input: n 1) remarks 4. the minimum and maximum values are calculated where t cyx = t cyk = 120 ns. chapter 2 78k/0 core 30 design manual a13195ej5v0dm (5) basic operation parameter symbol conditions min. typ. max. unit operates with main system clock 0.24 32 s cycle time (minimum instruction execution time) ? t cy operates with subsystem clock 40 122 125 s <44> t tih0 ti01, ti00 input high-/low-level width <45> t til0 2/f sam +0.1 note s ti51, ti50 input frequency <46> f ti5 010mhz <47> t tih5 ti51, ti50 input high-/low-level width <48> t til5 40 ns interrupt request input high-level width <49> t inth int11 to int0 1 s resetb low-level width <50> t rsl 10 s note f sam = f x , f x /4, or f x /64 can be selected by using bits 0 and 1 (prm00 and prm01) of the prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, f sam = f x /8. (6) serial interface (a) 3-wire serial i/o mode (sck31ob, sck30ob ... internal clock output) parameter symbol conditions min. typ. max. unit sck31ob, sck30ob cycle time <51> t kcy1 954 ns <52> t kh1 sck31ob, sck30ob high-/low-level width <53> t kl1 t kcy1 /2 ? 20 ns si31, si30 setup time (to sck31ob, sck30ob ) <54> t sik1 50 ns si31, si30 hold time (from sck31ob, sck30ob ) <55> t ksi1 70 ns delay time from sck31ob, sck30ob to so31, so30 output <56> t kso1 70 ns (b) 3-wire serial i/o mode (sck31ib, sck30ib ... external clock input) parameter symbol conditions min. typ. max. unit sck31ib, sck30ib cycle time <57> t kcy2 800 ns <58> t kh2 sck31ib, sck30ib high-/low-level width <59> t kl1 380 ns si31, si30 setup time (to sck31ib, sck30ib ) <60> t sik2 50 ns si31, si30 hold time (from sck31ib, sck30ib ) <61> t ksi2 70 ns delay time from sck31ib, sck30ib to so31, so30 output <62> t kso2 70 ns chapter 2 78k/0 core 31 design manual a13195ej5v0dm (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate ? 262144 bps (d) uart mode (infrared data transfer mode) parameter symbol conditions min. max. unit transfer rate ? 115200 bps permissible bit rate error ? 0.87 % number of output pulses ? 1.2 0.24/fbr s number of input pulses ? 4/f x s remark fbr: set baud rate (e) i 2 c bus mode standard mode high-speed mode parameter symbol min. max. min. max. unit scl0 clock frequency <63> f clk 0 100 0 400 khz bus free time (between stop and start conditions) <64> t buf 4.8 1.4 s hold time note <65> t hd : sta 4.1 0.7 s low-level width of scl0 clock <66> t low 5.0 1.25 s high-level width of scl0 clock <67> t high 5.0 1.25 s setup time of start/restart condition <68> t su : sta 4.8 0.7 s data setup time (reception) <69> t su : dat 00ns data hold time (transmission) <70> t hd : dat 0.72 3.5 0.48 1.0 s note the first clock pulse is created after this period in the start condition. caution the serial data line (sda0) and serial clock line (scl0) pins of serial interface (iic0) incorporated in the 78k/0 core are separated to input pins (sdai00, scli00) and output pins (sdao00, sclo00). therefore, when the configuration consists of external device and i 2 c bus, the circuit should be as shown in figure 2-1 (for details, refer to 78k/0 core user?s manual (a13142e)). chapter 2 78k/0 core 32 design manual a13195ej5v0dm figure 2-1. example of circuit construction of serial interface (iic0) input/output pin 2. 3. 5 low-voltage data retention characteristics of data memory in stop mode (t a = ? ? ? ? 40 to +85c) parameter symbol conditions min. typ. max. unit release signal set time <72> t srel 0 s released by resetb 0 ms oscillation stabilization wait time note <73> t wait released by interrupt request 0 ms note the user should ensure the lapse of the oscillation stabilization time if necessary. 2. 4 timing chart (1) clock timing sdao00 sdai00 sclo00 scli00 n-ch open drain output n-ch open drain output output control circuit 78k/0 core scl0 sda0 clkin (input) <1> <2> <3> chapter 2 78k/0 core 33 design manual a13195ej5v0dm (2) fetch timing 1 (when divider (f x /2) is used, no wait) (3) fetch timing 2 (when divider is not used, no wait) clkin (input) <16> <22> <4> <17> <22> <7> <6> <18> <23> <21> astb (output) <5> <5> <15> <20> <6> <19> a15 to a0 (output) din7 to din0 (input) rdb (output) hi-z hi-z clkin (input) <16> <22> <4> <17> <22> <7> <6> <18> <23> <21> astb (output) <5> <5> <15> <20> <6> <19> a15 to a0 (output) din7 to din0 (input) rdb (output) hi-z hi-z chapter 2 78k/0 core 34 design manual a13195ej5v0dm (4) read timing 1 (when data is accessed and when divider is used, no wait) (5) read timing 2 (when data is accessed and when divider is not used, no wait) clkin (input) <16> <24> <4> <17> <22> <7> <6> <18> <23> <21> astb (output) <5> <5> <15> <20> <6> <19> a15 to a0 (output) din7 to din0 (input) rdb (output) hi-z hi-z clkin (input) astb (output) a15 to a0 (output) din7 to din0 (input) rdb (output) <16> <24> <4> <17> <22> <7> <6> <18> <23> <21> <5> <5> <15> <20> <6> <19> hi-z hi-z chapter 2 78k/0 core 35 design manual a13195ej5v0dm (6) write timing 1 (when data is accessed and when divider is used, no wait) (7) write timing 2 (when data is accessed and when divider is not used, no wait) clkin (input) <16> <4> <7> <27> astb (output) <5> <5> <15> a15 to a0 (output) dout7 to dout0 (input) wrb (output) <14> <11> <13> <30> <29> <28> <11> <12> <25> <26> undefined undefined clkin (input) <16> <4> <7> <27> astb (output) <5> <5> <15> a15 to a0 (output) <14> <11> <13> <30> <29> <28> <11> <12> <25> <26> dout7 to dout0 (input) wrb (output) undefined undefined chapter 2 78k/0 core 36 design manual a13195ej5v0dm (8) external wait input fetch timing 1 (when divider is used, 1 wait) (9) external wait input fetch timing 2 (when divider is not used, 1 wait) clkin (input) astb (output) a15 to a0 (output) din7 to din0 (input) rdb (output) waitb (input) <9> <10> <37> <38> <35> <36> <31> <32> <39> <33> <34> <8> hi-z hi-z clkin (input) astb (output) a15 to a0 (output) din7 to din0 (input) rdb (output) waitb (input) <9> <8> <10> <37> <38> <35> <36> <31> <32> <39> <33> <34> hi-z hi-z chapter 2 78k/0 core 37 design manual a13195ej5v0dm (10) external wait input read timing 1 (when data is accessed and when divider is used, 1 wait) (11) external wait input read timing 2 (when data is accessed and when divider is not used, 1 wait) clkin (input) astb (output) a15 to a0 (output) din7 to din0 (input) rdb (output) waitb (input) <9> <10> <37> <38> <35> <36> <31> <32> <39> <33> <34> <8> hi-z clkin (input) astb (output) a15 to a0 (output) din7 to din0 (input) rdb (output) waitb (input) <9> <10> <37> <38> <35> <36> <31> <32> <39> <33> <34> <8> hi-z chapter 2 78k/0 core 38 design manual a13195ej5v0dm (12) external wait input write timing 1 (when data is accessed and when divider is used, 1 wait) (13) external wait input write timing 2 (when data is accessed and when divider is not used, 1 wait) clkin (input) astb (output) a15 to a0 (output) dout7 to dout0 (input) wrb (output) waitb (input) <9> <8> <10> <43> <42> <40> <32> <31> <33> <34> undefined <41> clkin (input) astb (output) a15 to a0 (output) dout7 to dout0 (input) wrb (output) waitb (input) <9> <8> <10> <43> <42> <40> <32> <31> <33> <34> <41> undefined chapter 2 78k/0 core 39 design manual a13195ej5v0dm (14) ti timing (15) interrupt request input timing (16) resetb input timing ti01,ti00 (input) <45> <44> 1/f ti5 ti51,ti50 (input) <48> <47> resetb (input) <50> int11 to int0 (input) <49> chapter 2 78k/0 core 40 design manual a13195ej5v0dm (17) serial transfer timing (a) 3-wire serial i/o mode remark n = 1, 0 (b) i 2 c bus mode sck3nob (output) sck3nib (input) <53>,<59> <52>,<58> <55>,<61> <54>,<60> si3n (input) so3n (output) <56>, <62> <51>,<57> input data output data undefined undefined scl0 <64> sda0 <66> <63> <67> <69> <65> <68> <65> <70> stop condition start condition stop condition restart condition chapter 2 78k/0 core 41 design manual a13195ej5v0dm (18) data retention timing (standby release signal: stop mode is released by interrupt request signal) (19) data retention timing (stop mode is released by resetb) v dd data retention mode standby release signal (interrupt request) <72> <73> v dddr stop mode halt mode operation mode execution of stop instruction v dd data retention mode resetb (input) <72> <73> v dddr stop mode halt mode execution of stop instruction operation mode internal reset operation 42 design manual a13195ej5v0dm chapter 3 v851 core the v851 core is a cpu core having peripheral functions such as a real-time pulse unit and serial interfaces. the instruction set of the v851 core is common to that of the v850 family tm 32-bit single-chip microcontrollers. 3. 1 outline ? cpu performance: 38 mips (@ 33 mhz operation) ? internal memory (rom can be removed.) mask rom: 48, 64, 96, 128, and 256 kb ram: 4, 8, 16, and 24 kb ? minimum instruction execution time: 30 ns (@ 33 mhz operation) ? external bus interface 16-bit data bus (din/dout separated) 24-bit address bus ? interrupt/exception external interrupt: 9 (including nmi) internal interrupt: 14 sources software exception: 32 sources exception trap: 1 source eight priority levels can be specified. ? real-time pulse unit 16-bit timer/event counter: 1 ch 16-bit interval timer: 1 ch ? serial interface asynchronous serial interface (uart): 1 ch clocked serial interface (csi): 1 ch ? power save function halt, stop, idle mode clock output stop function chapter 3 v851 core 43 design manual a13195ej5v0dm 3. 1. 1 symbol diagram number of grids 139k grids 156k grids (including wiring area) number of separation simulation patterns rom size ram size 0 byte (romless) 48 kb 64 kb 96 kb 128 kb 256 kb 4 kb na851m02 258.5k na851m32 270.6k na851m42 278.8k na851m62 295.2k na851m82 311.5k na851mg2 377.1k 8 kb na851m04 258.5k na851m34 270.6k na851m44 278.8k na851m64 295.2k na851m84 311.5k na851mg4 377.1k 16 kb na851m08 266.1k na851m38 278.2k na851m48 286.4k na851m68 302.8k na851m88 319.2k na851mg8 384.7k 24 kb na851m0c 266.1k na851m3c 278.2k na851m4c 286.4k na851m6c 302.8k na851m8c 319.2k na851mgc 384.7k remark the upper figure in each column of the above table indicates the part number and the lower figure indicates the total number of patterns. remarks chapter 3 v851 core 44 design manual a13195ej5v0dm in out clkin to10 ti1 hldakb hldrqb adoenb din(15:0) out astb out dstbb out rwb out rdb out out out in out out in out in out in in out out in wrb ubenb lbenb waitb a(23:0) adout(15:0) tclr1 to11 rxd ici(1:0) ico(1:0) in tbcenb in resetb clkout out oscen out mode0 in nmi in intp00 in intp01 in intp02 in intp03 in intp10 in intp11 in intp12 in intp13 in tbo (23:0) tbi (41:0) test bunri in in in out in si out in out out out txd so soenb sckinb in out mode1 in out st0 out st1 sckoutb sckoenb chapter 3 v851 core 45 design manual a13195ej5v0dm 3. 1. 2 pin capacitance (1) input pins pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) din15 0.025 1.925 sckinb 0.015 1.915 tbi24 0.023 1.923 din14 0.020 1.920 si 0.019 1.919 tbi23 0.024 1.924 din13 0.016 1.916 tbcenb 0.017 1.917 tbi22 0.015 1.915 din12 0.022 1.922 ti1 0.021 1.921 tbi21 0.017 1.917 din11 0.021 1.921 tclr1 0.028 1.928 tbi20 0.015 1.915 din10 0.021 1.921 rxd 0.013 1.913 tbi19 0.020 1.920 din9 0.024 1.924 waitb 0.171 2.071 tbi18 0.019 1.919 din8 0.018 1.918 nmi 0.015 1.915 tbi17 0.027 1.927 din7 0.015 1.915 resetb 0.027 1.927 tbi16 0.019 1.919 din6 0.021 1.921 ici1 0.013 1.913 tbi15 0.018 1.918 din5 0.016 1.916 ici0 0.013 1.913 tbi14 0.016 1.916 din4 0.014 1.914 tbi41 0.064 1.964 tbi13 0.018 1.918 din3 0.014 1.914 tbi40 0.023 1.923 tbi12 0.015 1.915 din2 0.014 1.914 tbi39 0.022 1.922 tbi11 0.014 1.914 din1 0.015 1.915 tbi38 0.016 1.916 tbi10 0.013 1.913 din0 0.033 1.933 tbi37 0.011 1.911 tbi9 0.014 1.914 clkin 0.020 1.920 tbi36 0.022 1.922 tbi8 0.016 1.916 hldrqb 0.137 2.037 tbi35 0.014 1.914 tbi7 0.019 1.919 intp13 0.014 1.914 tbi34 0.022 1.922 tbi6 0.013 1.913 intp12 0.013 1.913 tbi33 0.014 1.914 tbi5 0.017 1.917 intp11 0.014 1.914 tbi32 0.014 1.914 tbi4 0.019 1.919 intp10 0.014 1.914 tbi31 0.156 2.056 tbi3 0.020 1.920 intp03 0.016 1.916 tbi30 0.147 2.047 tbi2 0.019 1.919 intp02 0.014 1.914 tbi29 0.018 1.918 tbi1 0.020 1.920 intp01 0.021 1.921 tbi28 0.024 1.924 tbi0 0.038 1.938 intp00 0.014 1.914 tbi27 0.015 1.915 bunri 1.433 3.333 mode1 0.017 1.917 tbi26 0.022 1.922 test 1.740 3.640 mode0 0.017 1.917 tbi25 0.016 1.916 remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) chapter 3 v851 core 46 design manual a13195ej5v0dm (2) output pins pin name c max (pf) pin name c max (pf) pin name c max (pf) a23 to a0 6.570 oscen 13.340 st1 6.587 adoenb 13.072 rdb 6.570 st0 6.587 adout15 to 6.570 rwb 6.570 to11 4.993 adout0 sckoenb 4.993 to10 4.993 dstbb 6.570 sckoutb 3.300 txd 4.993 hldakb 6.570 so 4.775 ico1 6.587 astb 3.300 soenb 6.587 ico0 6.570 clkout 13.072 ubenb 6.587 tbo23 to tbo0 6.536 lbenb 6.587 wrb 6.570 chapter 3 v851 core 47 design manual a13195ej5v0dm 3. 2 resetb signal in view of the evaluations performed by nec, when the resetb signal is changed, do not synchronize it with the system clock?s rising and falling edges (see figure 3-1 ). figure 3-1. resetb signal input example 3. 3 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in test program execution. failure to do this will result in the propagation of undefined values. clkout (output) resetb (input) reset period chapter 3 v851 core 48 design manual a13195ej5v0dm 3. 4 pin functions (1/2) pin name i/o function to11, to10 output pulse signal output from timer 1. tclr1 input external clear signal input to timer 1. ti1 input external count clock input to timer 1. intp13 to intp10 input external capture trigger input to timer 1/external maskable interrupt request input. intp03 to intp00 input external maskable interrupt request input. nmi input non-maskable interrupt request input. so output serial transmit data output from csi. si input serial receive data input to csi. soenb output so pin control signal output. sckinb input serial clock input to csi. sckoutb output serial clock output from csi. sckoenb output signal output indicating input/output direction of serial clock of csi. txd output serial transmit data output from uart. rxd input serial receive data input to uart adout15 to adout0 output timer-division output of address/data when accessing external device. adoenb output adout15 to adout0 pins control signal output. din15 to din0 input data input when accessing external device. a23 to a0 output address output when accessing external device. lbenb output lower byte enable signal output of external data bus. ubenb output upper byte enable signal output of external data bus. rwb output external read/write status output. rdb output external read strobe output. wrb output external write strobe output. dstbb output external data strobe signal output. astb output external address strobe signal output. st1, st0 output external bus cycle status output. hldakb output bus hold acknowledge output. hldrqb input bus hold request input. waitb input inputs control signal that inserts wait states to bus cycle. resetb input system reset input. clkin input external clock input. clkout output internal system clock output. tbcenb input inputs control signal to time base counter (tbc). oscen output specifies operation of external osc. mode1, mode0 input specifies operation mode of v851 core. tbi41 to tbi0 input pin for test using test bus. tbo23 to tbo0 output test input chapter 3 v851 core 49 design manual a13195ej5v0dm (2/2) pin name i/o function bunri input pin for test using test bus. ico1, ico0 output nec reserved pin. ici1, ici0 input chapter 3 v851 core 50 design manual a13195ej5v0dm 3. 5 electrical specifications the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 3. 5. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 3. 5. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 30 ns 3. 5. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1a without rom, ram 0.4 0.5 ma/mhz supply current i dd1b in normal operation mode other than the above see (1) how to calculate the current consumption value of the v851 core i dd2 in halt mode 0.2 0.3 ma/mhz i dd3 in stop mode 1.0 15 a remark the typ. value is a reference value for when t a = 25c, v dd = 3.3 v. caution the current flow to the internal rom in the reset interval is a maximum 5 ma. (1) how to calculate the current consumption value of the v851 core the current consumption value (typ.) of the v851 core with internal rom and ram is defined by the following expression. i dd1b = i dd1a + i ddrom + i ddram i ? i ddrom : the current consumption value of internal rom ? i ddram : the current consumption value of internal ram chapter 3 v851 core 51 design manual a13195ej5v0dm the following is an example of how to calculate the current consumption value of the na851m82 (internal rom: 128 kb/internal ram: 4 kb). caution this current consumption calculation is for reference only; the values calculated herein are not guaranteed. conditions: v dd = 3.3 v = 33 mhz operation percentage of internal rom = 80% operation percentage of internal ram = 20% (the ratio of read operation to write operation = 1:1) internal ram read operation frequency (f r ) = 33 mhz internal ram write operation frequency (f w ) = 33 mhz the current consumption value when an operation is performed under the above conditions is calculated by the following expression. i dd1a = 0.4 = 0.4 33 = 13.2 [ma] ?<1> i ddrom note 1 = ( (2.2 + (v dd ? 2.7) 3.0) + (0.05 v dd ) ) operating ratio % = ( (2.2 + (3.3 ? 2.7) 3.0) + (0.05 3.3 33) ) 0.8 = 7.556 [ma] ?<2> i ddram (read) note 2 = 0.82 f r operating ratio % = 0.82 33 0.2 0.5 = 2.706 [ma] ?<3> i ddram (write) note 3 = 0.83 f w operating ratio % = 0.83 33 0.2 0.5 = 2.739 [ma] ?<4> from <3> and <4>, i ddram = (i ddram (read) + i ddram (write) ) = 2.706 + 2.739 = 5.445 [ma] ?<5> from <1>, <2>, and <5>, i dd1b = 13.2 + 7.556 + 5.445 = 26.201 [ma] therefore, from the above, the current consumption (typ.) of the na851m82 is 26.201 ma. notes 1. use the following expression regardless of the internal rom size (excepting romless versions). ( (2.2 + (v dd ? 2.7) 3.0) + (0.05 v dd ) ) operating ratio % notes 2. use the following expressions for 8 kb, 16 kb, and 24 kb internal ram sizes respectively. 8 kb: 2.55 f r operating ratio % 16 kb: 3.02 f r operating ratio % 24 kb: 3.34 f r operating ratio % notes 3. use the following expressions for 8 kb, 16 kb, and 24 kb internal ram sizes respectively. 8 kb: 2.41 f w operating ratio % 16 kb: 2.41 f w operating ratio % 24 kb: 2.62 f w operating ratio % chapter 3 v851 core 52 design manual a13195ej5v0dm 3. 5. 4 ac characteristics (t a = ? ? ? ? 40 to +85c, v dd = 3.3 v 0.3 v) (1) clock timing parameter symbol conditions min. max. unit clkin input cycle <1> t cyx 30 ns clkin input high-level width <2> t wxh 14 ns clkin input low-level width <3> t wxl 14 ns cpu operating frequency ? 033mhz clkout output cycle <4> t cyk 30 ns clkout high-level width <5> t wkh 0.5t cyk ? 5ns clkout low-level width <6> t wkl 0.5t cyk ? 5ns (2) reset timing parameter symbol conditions min. max. unit resetb high-level width <7> t wrsh 500 ns resetb low-level width <8> t wrsl on power application 500 ns clkin (input) clkout (output) <1>,<4> <2>,<5> <3>,<6> resetb (input) <7> <8> chapter 3 v851 core 53 design manual a13195ej5v0dm (3) read timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <9> t dka 3ns delay time from clkout to astb <11> t dkst 4ns delay time from clkout to dstbb <12> t dkd 3ns delay time from clkout to status <13> t dks 3ns data input setup time (to clkout ) <14> t sidk 2ns data input hold time (from clkout ) <15> t hkid 2ns waitb setup time (to clkout ) <16> t swtk 2ns waitb hold time (from clkout ) <17> t hkwt 2ns address setup time (to astb ) <19> t sast 0.5t ? 6ns address hold time (from astb ) <20> t hsta 0.5t ? 6ns delay time from clkout to lbenb <22> t dklb 3ns delay time from clkout to ubenb <23> t dkub 3ns delay time from astb to dstbb <24> t dstd 0.5t ? 6ns data input hold time (from dstbb ) <25> t hdid 0ns delay time from dstbb to address output <26> t dda (1 + i)t ns delay time from dstbb to astb <27> t ddsth 0.5t ? 6ns delay time from dstbb to astb <28> t ddstl (1.5 + i)t ? 6 ns status setup time (to astb ) <29> t ssst 0.5t ? 6ns status hold time (from astb ) <30> t hsts 0.5t ? 6ns dstbb low-level width <31> t wdl (1 + n)t ? 5ns astb high-level width <32> t wsth t ? 5ns waitb setup time (to address) <33> t sawt1 n 11.5t ? 11 ns <34> t sawt2 (1.5 + n)t ? 11 ns waitb hold time (from address) <35> t hawt1 n 1 1.5t + 6 ns <36> t hawt2 (1.5 + n)t + 6 ns waitb setup time (to astb ) <37> t sstwt1 n 1t ? 10 ns <38> t sstwt2 (1 + n)t ? 10 ns waitb hold time (from astb ) <39> t hstwt 1 n 1nt + 5 ns <40> t hstwt 2 (1 + n)t + 5 ns delay time from clkout to adoenb <41> t dkaden 3ns delay time from clkout to address/data output <42> t dkad 5ns remarks 1. t = t cyk remarks 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing changes when programmable wait cycles are inserted. remarks 3. i indicates the number of idle states (0 or 1) inserted after read cycle. remarks 4. be sure to satisfy at least one of data input hold times t hkid and t hdid . chapter 3 v851 core 54 design manual a13195ej5v0dm (3) read timing (2/2) clkout (output) <9> t1 t2 tw t3 a23 to a0 (output) adout15 to adout0 (output) din15 to din0 (input) astb (output) rwb (output) dstbb (output) rdb (output) st1, st0 (output) waitb (input) adoenb (output) <42> <42> <19> <14> <15> <26> <11> <32> <29> <37> <16> <17> <39> <38> <16> <17> <40> <36> <34> <35> <33> <28> <25> <11> <20> <12> <24> <12> <13> <13> <41> <31> <27> address address data lbenb (output) ubenb (output) <22>,<23> <22>,<23> <30> undefined undefined undefined chapter 3 v851 core 55 design manual a13195ej5v0dm (4) write timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <9> t dka 3ns delay time from clkout to astb <11> t dkst 4ns delay time from clkout to dstbb <12> t dkd 3ns delay time from clkout to status <13> t dks 3ns waitb setup time (to clkout ) <16> t swtk 2ns waitb hold time (from clkout ) <17> t hkwt 2ns address setup time (to astb ) <19> t sast 0.5t ? 6ns address hold time (from astb ) <20> t hsta 0.5t ? 6ns delay time from astb to dstbb <24> t dstd 0.5t ? 6ns delay time from dstbb to astb <27> t ddsth 0.5t ? 6ns status setup time (to astb ) <29> t ssst 0.5t ? 6ns status hold time (from astb ) <30> t hsts 0.5t ? 6ns dstbb low-level width <31> t wdl (1+n)t ? 5ns astb high-level width <32> t wsth t ? 5ns waitb setup time (to address) <33> t sawt1 n 11.5t ? 11 ns <34> t sawt2 (1.5 + n)t ? 11 ns waitb hold time (from address) <35> t hawt1 n 1 1.5t + 6 ns <36> t hawt2 (1.5 + n)t + 6 ns waitb setup time (to astb ) <37> t sstwt1 n 1t ? 10 ns <38> t sstwt2 (1 + n)t ? 10 ns waitb hold time (from astb ) <39> t hstwt 1 n 1nt + 5 ns <40> t hstwt 2 (1 + n)t + 5 ns delay time from clkout to adoenb <41> t dkaden 3ns delay time from clkout to address/data output <42> t dkad 5ns delay time from dstbb to data output <43> t ddod 5ns data output hold time (from clkout ) <44> t hkod 5ns data output setup time (to dstbb ) <45> t sodd (1 + n)t ? 5ns data output hold time (from dstbb ) <46> t hdod t ? 5ns remarks 1. t = t cyk remarks 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing changes when programmable wait cycles are inserted. chapter 3 v851 core 56 design manual a13195ej5v0dm (4) write timing (2/2) clkout (output) <9> t1 t2 tw t3 a23 to a0 (output) adout15 to adout0 (output) din15 to din0 (input) astb (output) rwb (output) dstbb (output) wrb (output) st1, st0 (output) waitb (input) adoenb (output) <42> <42> <19> <11> <32> <29> <37> <16> <17> <39> <38> <16> <17> <40> <36> <34> <35> <33> <30> <12> <12> <13> <13> <41> <45> <27> address data address undefined <44> <46> <11> <43> <31> <24> <20> chapter 3 v851 core 57 design manual a13195ej5v0dm (5) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrqb setup time (to clkout ) <47> t shqk 2ns hldrqb hold time (from clkout ) <48> t hkhq 2ns delay time from clkout to hldakb <49> t dkha 3ns hldrqb high-level width <50> t whqh t + 5 ns hldakb low-level width <51> t whal t ? 5ns delay time from hldrqb to hldakb <53> t dhqha1 (2n + 7.5)t + 11 ns delay time from hldrqb to hldakb <54> t dhqha2 1.5t + 11 ns remarks 1. t = t cyk remarks 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing changes when programmable wait cycles are inserted. chapter 3 v851 core 58 design manual a13195ej5v0dm (5) bus hold timing (2/2) undefined clkout (output) t2 t3 th th th th ti t1 hldrqb (input) hldakb (output) a23 to a0 (output) adout15 to adout0 (output) din15 to din0 (input) astb (output) rwb (output) dstbb (output) wrb (output) st1,st0 (output) ubenb (output) lbenb (output) <47> <48> <47> <50> <54> <53> <51> address data undefined undefined undefined undefined undefined <49> <49> chapter 3 v851 core 59 design manual a13195ej5v0dm (6) interrupt timing parameter symbol conditions min. max. unit nmi high-level width <55> t wnih 500 ns nmi low-level width <56> t wnil 500 ns intpmn high-level width <57> t with 3t + 10 ns intpmn low-level width <58> t witl 3t + 10 ns remarks 1. t = t cyk remarks 2. m = 1, 0 n = 3 to 0 remark m = 1, 0 n = 3 to 0 nmi (input) <55> <56> intpmn (input) <57> <58> chapter 3 v851 core 60 design manual a13195ej5v0dm (7) csi timing (a) master mode parameter symbol conditions min. max. unit sckoutb cycle <59> t cysk output 120 ns sckoutb high-level width <60> t wskh output 0.5 t cysk ? 10 ns sckoutb low-level width <61> t wskl output 0.5 t cysk ? 10 ns si setup time (to sckoutb ) <62> t ssisk 5ns si hold time (from sckoutb ) <63> t hsksi 5ns so delay time (from sckoutb ) <64> t dskso 5ns (b) slave mode parameter symbol conditions min. max. unit sckinb cycle <59> t cysk input 120 ns sckinb high-level width <60> t wskh input 30 ns sckinb low-level width <61> t wskl input 30 ns si setup time (to sckinb ) <62> t ssisk 5ns si hold time (from sckinb ) <63> t hsksi 5ns so delay time (from sckinb ) <64> t dskso 5ns sckinb (input) sckoutb (output) <60> <59> <61> <62> <63> undefined un- defined un- defined input data input data si (input) input data so (output) <64> output data <64> chapter 3 v851 core 61 design manual a13195ej5v0dm (8) rpu timing parameter symbol conditions min. max. unit ti1 high-level width <66> t wtih 3t + 10 ns ti1 low-level width <67> t wtil 3t + 10 ns tclr1 high-level width <68> t wtch 3t + 10 ns tclr1 low-level width <69> t wtcl 3t + 10 ns delay time from clkout to to <70> t dkto 5ns remark t = t cyk ti1 (input) <66> <67> tclr1 (input) <68> <69> clkout (output) <70> to (output) <70> 62 design manual a13195ej5v0dm chapter 4 v853 core the v853 core is a cpu core having peripheral functions such as a real-time pulse unit, pwm output, and serial interfaces. the instruction set of the v853 core is common to that of the v850 family 32-bit single-chip microcontrollers. 4. 1 outline ? cpu performance: 38 mips (@ 33 mhz operation) ? internal memory (rom can be removed.) mask rom: 48, 64, 96, 128, and 256 kb ram: 4, 8, 16, and 24 kb ? minimum instruction execution time: 30 ns (@ 33 mhz operation) ? external bus interface 16-bit data bus (din/dout separated) 24-bit address bus ? interrupt/exception external interrupt: 17 (including nmi) internal interrupt: 31 sources software exception: 32 sources exception trap: 1 source eight priority levels can be specified. ? real-time pulse unit 16-bit timer/event counter: 4 chs 16-bit interval timer: 1 ch ? serial interface asynchronous serial interface (uart) clocked serial interface (csi) uart/csi: 2 chs csi: 2 chs dedicated baud rate generator: 3 chs ? pwm (pulse width modulation) 8/9/10/12-bit resolution pwm: 2 chs ? power save function halt, stop, idle mode clock output stop function chapter 4 v853 core 63 design manual a13195ej5v0dm 4. 1. 1 symbol diagram number of grids 239k grids 262k grids (including wiring area) number of separation simulation patterns rom size ram size 0 byte (romless) 48 kb 64 kb 96 kb 128 kb 256 kb 4 kb na853m02 306.0k na853m32 318.4k na853m42 326.6k na853m62 342.9k na853m82 359.3k na853mg2 424.8k 8 kb na853m04 306.0k na853m34 318.4k na853m44 326.6k na853m64 342.9k na853m84 359.3k na853mg4 424.8k 16 kb na853m08 313.2k na853m38 325.6k na853m48 333.8k na853m68 350.1k na853m88 366.5k na853mg8 432.0k 24 kb na853m0c 313.2k na853m3c 325.6k na853m4c 333.8k na853m6c 350.1k na853m8c 366.5k na853gc 432.0k remark the upper figure in each column of the above table indicates the part number and the lower figure indicates the total number of patterns. remarks chapter 4 v853 core 64 design manual a13195ej5v0dm in clkin sck0outb rxdsi0 hldakb hldrqb adoenb din(15:0) out astb out dstbb out rwb out rdb out out out in out out in out in out out in out in out out wrb ubenb lbenb waitb a(23:0) adout(15:0) txdso0 sck0inb txdso0enb sck0oenb ici0 ici1 to141 pwm0 in tbcenb in resetb clkout out oscen out mode0 in nmi in intp110 in intp111 in intp112 in intp113 in intp120 in intp121 in intp122 in intp123 in intp130 in intp131 in intp132 in intp133 intp140 in intp141 in intp142 in intp143 in tclr11 in ti11 in to110 out to111 out tclr12 in ti12 in to120 out to121 out tclr13 in ti13 in to130 out to131 out tclr14 in ti14 in to140 out tbo (39:0) tbi (56:0) test bunri in in in out out out in pwm1 out sck1outb rxdsi1 out in out in out out txdso1 sck1inb txdso1enb sck1oenb sck2outb si2 out in out in out out so2 sck2inb so2enb sck2oenb sck3outb si3 out in out in out out so3 sck3inb so3enb sck3oenb in in chapter 4 v853 core 65 design manual a13195ej5v0dm 4. 1. 2 pin capacitance (1) input pins (1/2) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) din15 0.067 1.967 ti12 0.013 1.913 tbi47 0.038 1.938 din14 0.094 1.994 tclr12 0.047 1.947 tbi46 0.017 1.917 din13 0.075 1.975 intp113 0.081 1.981 tbi45 0.085 1.985 din12 0.097 1.997 intp112 0.082 1.982 tbi44 0.020 1.920 din11 0.068 1.968 intp111 0.099 1.999 tbi43 0.068 1.968 din10 0.066 1.966 intp110 0.110 2.010 tbi42 0.016 1.916 din9 0.066 1.966 ti11 0.051 1.951 tbi41 0.020 1.920 din8 0.066 1.966 tclr11 0.072 1.972 tbi40 0.014 1.914 din7 0.067 1.967 si3 0.017 1.917 tbi39 0.007 1.907 din6 0.068 1.968 sck3inb 0.016 1.916 tbi38 0.016 1.916 din5 0.070 1.970 si2 0.035 1.935 tbi37 0.018 1.918 din4 0.072 1.972 sck2inb 0.044 1.944 tbi36 0.009 1.909 din3 0.094 1.994 rxdsi1 0.017 1.917 tbi35 0.013 1.913 din2 0.066 1.966 sck1inb 0.027 1.927 tbi34 0.007 1.907 din1 0.068 1.968 rxdsi0 0.035 1.935 tbi33 0.008 1.908 din0 0.067 1.967 sck0inb 0.017 1.917 tbi32 0.008 1.908 hldrqb 0.267 2.167 nmi 0.034 1.934 tbi31 0.009 1.909 waitb 0.139 2.039 resetb 0.017 1.917 tbi30 0.046 1.946 intp143 0.100 2.000 clkin 0.051 1.951 tbi29 0.041 1.941 intp142 0.113 2.013 ici1 0.017 1.917 tbi28 0.039 1.939 intp141 0.115 2.015 ici0 0.023 1.923 tbi27 0.018 1.918 intp140 0.132 2.032 mode 0.035 1.935 tbi26 0.016 1.916 ti14 0.015 1.915 tbcenb 0.025 1.925 tbi25 0.017 1.917 tclr14 0.196 2.096 test 3.041 4.941 tbi24 0.052 1.952 intp133 0.116 2.016 bunri 0.078 1.978 tbi23 0.203 2.103 intp132 0.069 1.969 tbi56 0.015 1.915 tbi22 0.037 1.937 intp131 0.100 2.000 tbi55 0.067 1.967 tbi21 0.052 1.952 intp130 0.108 2.008 tbi54 0.019 1.919 tbi20 0.051 1.951 ti13 0.013 1.913 tbi53 0.055 1.955 tbi19 0.018 1.918 tclr13 0.035 1.935 tbi52 0.019 1.919 tbi18 0.040 1.940 intp123 0.057 1.957 tbi51 0.068 1.968 tbi17 0.023 1.923 intp122 0.054 1.954 tbi50 0.142 2.042 tbi16 0.016 1.916 intp121 0.043 1.943 tbi49 0.240 2.140 tbi15 0.069 1.969 intp120 0.059 1.959 tbi48 0.016 1.916 tbi14 0.072 1.972 remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) chapter 4 v853 core 66 design manual a13195ej5v0dm (2/2) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) tbi13 0.074 1.974 tbi8 0.066 1.966 tbi3 0.084 1.984 tbi12 0.100 2.000 tbi7 0.075 1.975 tbi2 0.067 1.967 tbi11 0.068 1.968 tbi6 0.067 1.967 tbi1 0.069 1.969 tbi10 0.067 1.967 tbi5 0.071 1.971 tbi0 0.068 1.968 tbi9 0.071 1.971 tbi4 0.068 1.968 remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) chapter 4 v853 core 67 design manual a13195ej5v0dm (2) output pins pin name c max (pf) pin name c max (pf) pin name c max (pf) a23 6.565 adout0 6.565 tbo38 6.516 a22 6.562 lbenb 6.461 tbo37 6.271 a21 6.563 ubenb 6.500 tbo36 6.516 a20 6.558 rwb 6.532 tbo35 6.535 a19 6.567 dstbb 6.541 tbo34 6.531 a18 6.536 rdb 6.517 tbo33 6.534 a17 6.539 wrb 6.532 tbo32 6.530 a16 6.566 astb 6.553 tbo31 6.528 a15 6.512 adoenb 6.553 tbo30 6.511 a14 6.561 hldakb 6.444 tbo29 6.533 a13 6.570 to141 6.569 tbo28 6.513 a12 6.569 to140 6.569 tbo27 3.301 a11 6.557 to131 6.475 tbo26 6.452 a10 6.567 to130 6.569 tbo25 6.404 a9 6.567 to121 6.535 tbo24 6.501 a8 6.570 to120 6.567 tbo23 6.489 a7 6.554 to111 6.539 tbo22 6.443 a6 6.561 to110 6.547 tbo21 6.433 a5 6.560 so3 6.560 tbo20 6.523 a4 6.552 so3enb 6.568 tbo19 3.313 a3 6.536 sck3outb 6.564 tbo18 3.295 a2 6.569 sck3oenb 6.565 tbo17 3.313 a1 6.568 so2 6.569 tbo16 3.295 a0 6.498 so2enb 6.569 tbo15 6.479 adout15 6.519 sck2outb 6.569 tbo14 6.526 adout14 6.558 sck2oenb 6.569 tbo13 6.448 adout13 6.569 txdso1 6.568 tbo12 6.533 adout12 6.557 txdso1enb 6.567 tbo11 6.460 adout11 6.560 sck1outb 6.569 tbo10 6.487 adout10 6.532 sck1oenb 6.569 tbo9 6.513 adout9 6.561 txdso0 6.548 tbo8 6.516 adout8 6.570 txdso0enb 6.563 tbo7 6.468 adout7 6.568 sck0outb 6.540 tbo6 6.535 adout6 6.568 sck0oenb 6.536 tbo5 6.535 adout5 6.570 pwm1 6.569 tbo4 6.507 adout4 6.544 pwm0 6.569 tbo3 6.533 adout3 6.569 clkout 13.063 tbo2 6.513 adout2 6.569 oscen 6.337 tbo1 6.496 adout1 6.568 tbo39 3.308 tbo0 6.509 chapter 4 v853 core 68 design manual a13195ej5v0dm 4. 2 resetb signal in view of the evaluations performed by nec, when the resetb signal is changed, do not synchronize it with the system clock?s rising and falling edges (see figure 4-1 ). figure 4-1. resetb signal input example 4. 3 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in test program execution. failure to do this will result in the propagation of undefined values. clkout (output) resetb (input) reset period chapter 4 v853 core 69 design manual a13195ej5v0dm 4. 4 pin functions (1/2) pin name i/o function to141, to140 output pulse signal output from timer 1 (tm14). to131, to130 output pulse signal output from timer 1 (tm13). to121, to120 output pulse signal output from timer 1 (tm12). to111, to110 output pulse signal output from timer 1 (tm11). tclr14 input external clear signal input to timer 1 (tm14). tclr13 input external clear signal input to timer 1 (tm13). tclr12 input external clear signal input to timer 1 (tm12). tclr11 input external clear signal input to timer 1 (tm11). ti14 input external count clock input to timer 1 (tm14). ti13 input external count clock input to timer 1 (tm13). ti12 input external count clock input to timer 1 (tm12). ti11 input external count clock input to timer 1 (tm11). intp143 to intp140 input external capture trigger input to timer 1 (tm14)/external maskable interrupt request input. intp133 to intp130 input external capture trigger input to timer 1 (tm13)/external maskable interrupt request input. intp123 to intp120 input external capture trigger input to timer 1 (tm12)/external maskable interrupt request input. intp113 to intp110 input external capture trigger input to timer 1 (tm11)/external maskable interrupt request input. nmi input non-maskable interrupt request input. pwm1, pwm0 output pulse output from pwm. so3 output serial transmit data output from csi3. so2 output serial transmit data output from csi2. txdso1 output serial transmit data output from uart1/serial transmit data output from csi1. txdso0 output serial transmit data output from uart0/serial transmit data output from csi0. si3 input serial reception data input to csi3. si2 input serial reception data input to csi2. rxdsi1 input serial reception data input to uart1/serial reception data input to csi1. rxdsi0 input serial reception data input to uart0/serial reception data input to csi0. so3enb output so3 pin control signal output. so2enb output so2 pin control signal output. txdso1enb output txdso1 pin control signal output. txdso0enb output txdso0 pin control signal output. sck3inb input serial clock input to csi3. sck2inb input serial clock input to csi2. sck1inb input serial clock input to csi1. sck0inb input serial clock input to csi0. sck3outb output serial clock output from csi3. sck2outb output serial clock output from csi2. chapter 4 v853 core 70 design manual a13195ej5v0dm (2/2) pin name i/o function sck1outb output serial clock output from csi1. sck0outb output serial clock output from csi0. sck3oenb output signal output indicating input/output direction of serial clock of csi3. sck2oenb output signal output indicating input/output direction of serial clock of csi2. sck1oenb output signal output indicating input/output direction of serial clock of csi1. sck0oenb output signal output indicating input/output direction of serial clock of csi0. adout15 to adout0 output timer-division output of address/data when accessing external device. adoenb output adout15 to adout0 pins control signal output. din15 to din0 input data input when accessing external device. a23 to a0 output address output when accessing external device. lbenb output lower byte enable signal output of external data bus. ubenb output upper byte enable signal output of external data bus. rwb output external read/write status output. rdb output external read strobe output. wrb output external write strobe output. dstbb output external data strobe signal output. astb output external address strobe signal output. hldakb output bus hold acknowledge output. hldrqb input bus hold request input. waitb input inputs control signal that inserts wait states to bus cycle. resetb input system reset input. clkin input external clock input. clkout output internal system clock output. tbcenb input inputs control signal to time base counter (tbc). oscen output specifies operation of external osc. mode input specifies operation mode of v853 core. tbi56 to tbi0 input pin for test using test bus. tbo39 to tbo0 output test input bunri input ici1, ici0 output nec reserved pin. chapter 4 v853 core 71 design manual a13195ej5v0dm 4. 5 electrical specifications the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 4. 5. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 4. 5. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 30 ns 4. 5. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1a without rom, ram 0.6 0.8 ma/mhz supply current i dd1b in normal operation mode other than the above see (1) how to calculate the current consumption value of the v853 core i dd2 in halt mode 0.3 0.4 ma/mhz i dd3 in stop mode 1.0 30 a remark the typ. value is a reference value for when t a = 25c, v dd = 3.3 v. caution the current flow to the internal rom in the reset interval is a maximum 5 ma. (1) how to calculate the current consumption value of the v853 core the current consumption value (typ.) of the v853 core with internal rom and ram is defined by the following expression. i dd1b = i dd1a + i ddrom + i ddram i ? i ddrom : the current consumption value of internal rom ? i ddram : the current consumption value of internal ram chapter 4 v853 core 72 design manual a13195ej5v0dm the following is an example of how to calculate the current consumption value of the na853m82 (internal rom: 128 kb/internal ram: 4kb). caution this current consumption calculation is for reference only; the values calculated herein are not guaranteed. conditions: v dd = 3.3 v = 33 mhz operation percentage of internal rom = 80% operation percentage of internal ram = 20% (the ratio of read operation to write operation = 1:1) internal ram read operation frequency (f r ) = 33 mhz internal ram write operation frequency (f w ) = 33 mhz the current consumption value when an operation is performed under the above conditions is calculated by the following expression. i dd1a = 0.6 = 0.6 33 = 19.8 [ma] ?<1> i ddrom note 1 = ( (2.2 + (v dd ? 2.7) 3.0) + (0.05 v dd ) ) operating ratio % = ( (2.2 + (3.3 ? 2.7) 3.0) + (0.05 3.3 33) ) 0.8 = 7.556 [ma] ?<2> i ddram (read) note 2 = 0.82 f r operating ratio % = 0.82 33 0.2 0.5 = 2.706 [ma] ?<3> i ddram (write) note 3 = 0.83 f w operating ratio % = 0.83 33 0.2 0.5 = 2.739 [ma] ?<4> from <3> and <4>, i ddram = (i ddram (read) + i ddram (write) ) = 2.706 + 2.739 = 5.445 [ma] ?<5> from <1>, <2>, and <5>, i dd1b = 19.8 + 7.556 + 5.445 = 32.801 [ma] therefore, from the above, the current consumption (typ.) of the na853m82 is 32.801 ma. notes 1. use the following expression regardless of the internal rom size (excepting romless versions). ( (2.2 + (v dd ? 2.7) 3.0) + (0.05 v dd ) ) operating ratio % notes 2. use the following expressions for 8 kb, 16 kb, and 24 kb internal ram sizes respectively. 8 kb: 2.55 f r operating ratio % 16 kb: 3.02 f r operating ratio % 24 kb: 3.34 f r operating ratio % notes 3. use the following expressions for 8 kb, 16 kb, and 24 kb internal ram sizes respectively. 8 kb: 2.41 f w operating ratio % 16 kb: 2.41 f w operating ratio % 24 kb: 2.62 f w operating ratio % chapter 4 v853 core 73 design manual a13195ej5v0dm 4. 5. 4 ac characteristics (t a = ? ? ? ? 40 to +85c, v dd = 3.3 v 0.3 v) (1) clock timing parameter symbol conditions min. max. unit clkin input cycle <1> t cyx 30 ns clkin input high-level width <2> t wxh 14 ns clkin input low-level width <3> t wxl 14 ns cpu operating frequency ? 033mhz clkout output cycle <4> t cyk 30 ns clkout high-level width <5> t wkh 0.5t cyk ? 5ns clkout low-level width <6> t wkl 0.5t cyk ? 5ns (2) reset timing parameter symbol conditions min. max. unit resetb high-level width <7> t wrsh 500 ns resetb low-level width <8> t wrsl on power application 500 ns clkin (input) clkout (output) <1>,<4> <2>,<5> <3>,<6> resetb (input) <7> <8> chapter 4 v853 core 74 design manual a13195ej5v0dm (3) read timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <9> t dka 3ns delay time from clkout to astb <10> t dkst 4ns delay time from clkout to dstbb <11> t dkd 3ns data input setup time (to clkout ) <12> t sidk 2ns data input hold time (from clkout ) <13> t hkid 2ns waitb setup time (to clkout ) <14> t swtk 2ns waitb hold time (from clkout ) <15> t hkwt 2ns address setup time (to astb ) <17> t sast 0.5t ? 6ns address hold time (from astb ) <18> t hsta 0.5t ? 6ns delay time from clkout to lbenb <19> t dklb 3ns delay time from clkout to ubenb <20> t dkub 3ns delay time from astb to dstbb <21> t dstd 0.5t ? 6ns data input hold time (from dstbb ) <22> t hdid 0ns delay time from dstbb to address output <23> t dda (1 + i)t ns delay time from dstbb to astb <24> t ddsth 0.5t ? 6ns delay time from dstbb to astb <25> t ddstl (1.5 + i)t ? 6 ns dstbb low-level width <26> t wdl (1 + n)t ? 5ns astb high-level width <27> t wsth t ? 5ns waitb setup time (to address) <28> t sawt1 n 11.5t ? 11 ns <29> t sawt2 (1.5 + n)t ? 11 ns waitb hold time (from address) <30> t hawt1 n 11.5t + 6 ns <31> t hawt2 (1.5 + n)t + 6 ns waitb setup time (to astb ) <32> t sstwt1 n 1t ? 10 ns <33> t sstwt2 (1 + n)t ? 10 ns waitb hold time (from astb ) <34> t hstwt1 n 1nt + 5 ns <35> t hstwt2 (1 + n)t + 5 ns delay time from clkout to adoenb <36> t dkaden 3ns delay time from clkout to address/data output <37> t dkad 5ns remarks 1. t = t cyk remarks 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing changes when programmable wait cycles are inserted. remarks 3. i indicates the number of idle states (0 or 1) inserted after read cycle. remarks 4. be sure to satisfy at least one of data input hold times t hkid and t hdid . chapter 4 v853 core 75 design manual a13195ej5v0dm (3) read timing (2/2) clkout (output) <9> t1 t2 tw t3 a23 to a0 (output) adout15 to adout0 (output) din15 to din0 (input) astb (output) rwb (output) dstbb (output) rdb (output) waitb (input) adoenb (output) <37> <37> <17> <12> <13> <23> <10> <27> <32> <14> <15> <34> <33> <14> <15> <35> <31> <29> <30> <28> <25> <22> <10> <18> <11> <21> <11> <36> <26> <24> address address data lbenb (output) ubenb (output) <19>,<20> <19>,<20> undefined undefined undefined chapter 4 v853 core 76 design manual a13195ej5v0dm (4) write timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <9> t dka 3ns delay time from clkout to astb <10> t dkst 4ns delay time from clkout to dstbb <11> t dkd 3ns waitb setup time (to clkout ) <14> t swtk 2ns waitb hold time (from clkout ) <15> t hkwt 2ns address setup time (to astb ) <17> t sast 0.5t ? 6ns address hold time (from astb ) <18> t hsta 0.5t ? 6ns delay time from astb to dstbb <21> t dstd 0.5t ? 6ns delay time from dstbb to astb <24> t ddsth 0.5t ? 6ns dstbb low-level width <26> t wdl (1 + n)t ? 5ns astb high-level width <27> t wsth t ? 5ns waitb setup time (to address) <28> t sawt1 n 1 1.5t ? 11 ns <29> t sawt2 (1.5 + n)t ? 11 ns waitb hold time (from address) <30> t hawt1 n 1 1.5t + 6 ns <31> t hawt2 (1.5 + n)t + 6 ns waitb setup time (to astb ) <32> t sstwt1 n 1t ? 10 ns <33> t sstwt2 (1 + n)t ? 10 ns waitb hold time (from astb ) <34> t hstwt1 n 1nt + 5 ns <35> t hstwt2 (1 + n)t + 5 ns delay time from clkout to adoenb <36> t dkaden 3ns delay time from clkout to address/data output <37> t dkad 5ns delay time from dstbb to data output <38> t ddod 5ns data output hold time (from clkout ) <39> t hkod 5ns data output setup time (to dstbb ) <40> t sodd (1 + n)t ? 5ns data output hold time (from dstbb ) <41> t hdod t ? 5ns remarks 1. t = t cyk remarks 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing changes when programmable wait cycles are inserted. chapter 4 v853 core 77 design manual a13195ej5v0dm (4) write timing (2/2) clkout (output) <9> t1 t2 tw t3 a23 to a0 (output) adout15 to adout0 (output) din15 to din0 (input) astb (output) rwb (output) dstbb (output) wrb (output) waitb (input) adoenb (output) <37> <37> <17> <10> <27> <32> <14> <15> <34> <33> <14> <15> <35> <31> <29> <30> <28> <11> <11> <36> <40> <24> address data address undefined <39> <41> <10> <38> <21> <18> <26> chapter 4 v853 core 78 design manual a13195ej5v0dm (5) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrqb setup time (to clkout ) <42> t shqk 2ns hldrqb hold time (from clkout ) <43> t hkhq 2ns delay time from clkout to hldakb <44> t dkha 3ns hldrqb high-level width <45> t whqh t + 5 ns hldakb low-level width <46> t whal t ? 5ns delay time from hldrqb to hldakb <47> t dhqha1 (2n + 7.5)t + 11 ns delay time from hldrqb to hldakb <48> t dhqha2 1.5t + 11 ns remarks 1. t = t cyk remarks 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing changes when programmable wait cycles are inserted. chapter 4 v853 core 79 design manual a13195ej5v0dm (5) bus hold timing (2/2) undefined clkout (output) t2 t3 th th th th ti t1 hldrqb (input) hldakb (output) a23 to a0 (output) adout15 to adout0 (output) din15 to din0 (input) astb (output) rwb (output) dstbb (output) wrb (output) <42> <43> <42> <45> <48> <47> <46> address data undefined undefined undefined <44> <44> ubenb (output) lbenb (output) undefined chapter 4 v853 core 80 design manual a13195ej5v0dm (6) interrupt timing parameter symbol conditions min. max. unit nmi high-level width <49> t wnih 500 ns nmi low-level width <50> t wnil 500 ns intp1mn high-level width <51> t with 3t + 10 ns intp1mn low-level width <52> t witl 3t + 10 ns remarks 1. t = t cyk remarks 2. m = 4 to 1 n = 3 to 0 remark m = 4 to 1 n = 3 to 0 nmi (input) <49> <50> intp1mn (input) <51> <52> 81 design manual a13195ej5v0dm [memo] chapter 4 v853 core 82 design manual a13195ej5v0dm (7) csi timing (1/2) (a) master mode parameter symbol conditions min. max. unit scknoutb cycle <53> t cysk output 120 ns scknoutb high-level width <54> t wskh output 0.5 t cysk ? 10 ns scknoutb low-level width <55> t wskl output 0.5 t cysk ? 10 ns si3, si2, rxdsi1, rxdsi0 setup time (to scknoutb ) <56> t ssisk 5ns si3, si2, rxdsi1, rxdsi0 hold time (from scknoutb ) <57> t hsksi 5ns so3, so2, txdso1, txdso0 delay time (from scknoutb ) <58> t dskso 5ns remark n = 3 to 0 (b) slave mode parameter symbol conditions min. max. unit sckninb cycle <53> t cysk input 120 ns sckninb high-level width <54> t wskh input 30 ns sckninb low-level width <55> t wskl input 30 ns si3, si2, rxdsi1, rxdsi0 setup time (to sckninb ) <56> t ssisk 5ns si3, si2, rxdsi1, rxdsi0 hold time (from sckninb ) <57> t hsksi 5ns so3, so2, txdso1, txdso0 delay time (from sckninb ) <58> t dskso 5ns remark n = 3 to 0 chapter 4 v853 core 83 design manual a13195ej5v0dm (7) csi timing (2/2) remark n = 3 to 0 <54> <53> <55> <56> <57> undefined un- defined un- defined input data input data si3, si2, rxdsi1, rxdsi0 (input) input data <58> output data <58> sckninb (input) scknoutb (output) so3, so2, txdso1, txdso0 (output) chapter 4 v853 core 84 design manual a13195ej5v0dm (8) rpu timing parameter symbol conditions min. max. unit ti1n high-level width <60> t wtih 3t + 10 ns ti1n low-level width <61> t wtil 3t + 10 ns tclr1n high-level width <62> t wtch 3t + 10 ns tclr1n low-level width <63> t wtcl 3t + 10 ns delay time from clkout to to1nm <64> t dkto 5ns remarks 1. t = t cyk remarks 2. n = 4 to 1 m = 1, 0 remark n = 4 to 1 remark n = 4 to 1 m = 1, 0 ti1n (input) <60> <61> tclr1n (input) <62> <63> clkout (output) to1nm (output) <64> <64> chapter 4 v853 core 85 design manual a13195ej5v0dm (9) pwm timing parameter symbol conditions min. max. unit delay time from clkout to pwmn <65> t dkpwm 3ns remark n = 1, 0 remark n = 1, 0 clkout (output) pwmn (output) <65> <65> 86 design manual a13195ej5v0dm chapter 5 v30mx the v30mx is an asic original cpu core that has improved the bus efficiency by separating the address and data buses of nec?s original microprocessor ? pd70116h? (commonly known as v30hl?). as the instruction set is the same as v30hl, v30mx can be used without making any program changes. 5. 1 outline ? complete static circuit configuration and simplified standby and clock stop. ? low power consumption ? minimum instruction execution time: 60 ns (33 mhz, 3.3 v) ? on-chip lim ems 4.0 supporting register ? abundant memory addressing modes ? fourteen 16-bit register sets ? 101 kinds of instruction sets (complete compatibility with pd70116h) ? high speed execution of address calculation chapter 5 v30mx 87 design manual a13195ej5v0dm 5. 1. 1 symbol diagram number of grids 177k grids 228k grids (including wiring area) number of separation simulation patterns 80k emsren clko hldak in ei(3:0) out eo(8:0) out cnt1 out cnt2 out out out out out out out ps0 ps1 intakb bufrbw bufenb in ready in int pollb in nmi in clk in a(23:0) out ubeb out rdb out qs0 out qs1 out buslockb out bs0 out bs1 out bs2 out tbo (71:0) tbi (27:0) test bunri in in in out in hldrq in out ps2 out ps3 reset in d(15:0) io miob out wrb out out astb out dc chapter 5 v30mx 88 design manual a13195ej5v0dm 5. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) clk 0.033 1.933 pollb 0.033 1.933 ei3 to ei0 0.033 1.933 ready 0.033 1.933 emsren 0.033 1.933 reset 0.033 1.933 hldrq 0.033 1.933 tbi27 to tbi0 0.033 1.932 int 0.033 1.933 test 0.033 1.933 nmi 0.033 1.933 bunri 0.039 1.939 (2) output pins pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) a23 to a0 4.001 0.063 1.963 eo8 to eo0 5.421 ?? astb 5.421 ?? hldak 5.421 ?? bs2 to bs0 4.007 0.063 1.963 intakb 5.421 ?? bufenb 4.007 0.063 1.963 miob 4.007 0.063 1.963 bufrbw 4.007 0.063 1.963 ps3 to ps0 5.421 ?? buslockb 4.007 0.063 1.963 qs1, qs0 5.421 ?? clko 5.421 ?? rdb 4.007 0.063 1.963 cnt1 5.421 ?? ubeb 4.007 0.063 1.963 cnt2 5.421 ?? wrb 4.007 0.063 1.963 dc 5.421 ?? tbo71 to tbo0 4.007 0.063 1.963 (3) input/output pins pin name c max (pf) c in (pf) c inewl (pf) do15 to do0 4.007 0.096 1.996 chapter 5 v30mx 89 design manual a13195ej5v0dm 5. 2 notes for initialization (1) internal gate initialization method although the initial state of flip-flops does not cause a problem in the actual product, it has been known to do so during simulation. to avoid such problems, portions that cannot be initialized at a usual reset are initialized using the following methods. (a) verilog-xl tm as initialization is carried out automatically during simulation, there is no special need to do anything. (b) v.sim tm input the following command when executing simulation. command>iv instance-name/_u248:n01 = 1 if this command is set in the additional-command file, it will save the necessity of re-typing it each time simulation is executed. (2) inputting the initialization pattern from the test pin is not necessary. (3) the initialization pattern is input from the normal pin in the following manner. (a) hardware reset input logic 1 of at least four system clock (clock input to the clk pin) cycles to the reset pin. the v30mx executes instructions from address 0ffff0h when logic 0 is input to the reset pin and the reset is released. (b) instruction input input instructions as necessary after the hardware reset is released. instructions tend to become long (from several hundred bytes to several kb) and the cpu instruction read timing is then difficult to catch, so use a method that will store the total chip simulation program in the memory. chapter 5 v30mx 90 design manual a13195ej5v0dm 5. 3 notes for pattern generation and circuit designing 5. 3. 1 handling 3-state outputs 3-state output pins such as rdb and wrb (refer to 5. 4 pin functions for the 3-state output pins) become high impedance when the cpu is put on hold. if a floating level is supplied to a functional cell connected to a 3-state pin, errors and overlapping current due to a middle level input may occur. use the cnt2 and cnt1 pins to avoid high impedance and ensure that a floating level is not input directly. 5. 3. 2 reset signal the reset signal is executed from an instruction in the ffff0h address after the high levels of at least four clocks have been input to the reset pin, and upon the release of the reset following the input of the low levels. be aware that if the variable timing of the reset signal conflicts with the clock rise, a timing error will be generated and the reset operation may not run normally. the reset input must be set to low level when the reset is released. figure 5-1. reset signal input example 5. 3. 3 clk input a cpu reset occurs only when the clk input toggles. care should be taken when a frequency divider is inserted at the clk input of the cpu. (1) correct (2) incorrect r q t source clock clk reset system reset frequency d ivider reset r q t source clock clk reset system reset a system reset occurs, after the frequency division period reset is released. with this circuit, no reset can occur. clk (input) reset (input) reset period reset released chapter 5 v30mx 91 design manual a13195ej5v0dm 5. 3. 4 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in test program execution. take particular care not to overlook the stack pointer (sp). to minimize the execution time, avoid using subroutines as much as possible. 5. 3. 5 restriction of test program size the number of execution steps in the test program will ultimately determine the length of the test pattern, so try to reduce the number of these steps. make sure the number of patterns in the execution steps does not exceed 64000 (note that this is not the number of execution steps). to do this, ensure that the test program size is no more than 8 kb. if the test program contains loops, however, the number of patterns in the execution steps can exceed 64000, even if the test program size is 8 kb or less. note that the value of 8 kb is only a rough estimate. 5. 3. 6 segment specification in the test program the v30mx can use 16 mb of address space in the ems mode. however, as it is necessary to load the test program in an address that consists of eight consecutive kb, code segment specification should be carried out once only. for similar reasons, data and stack segment specification should also be carried out once only. 5. 3. 7 timing verification input timing verification methods vary depending on the simulator used. for verilog-xl, input timing verification is performed at execution, but for v.sim, no error message is output even if the input error ocurred at execution. for v.sim, be sure to verify by executing the opencad tm menu ?megamacro timing check?. if other simulators are used, contact nec for verification methods. chapter 5 v30mx 92 design manual a13195ej5v0dm 5. 4 pin functions pin name i/o function a23 to a0 3-state output address output d15 to d0 input/output data input/output ubeb 3-state output upper byte enable signal output of data bus rdb 3-state output read strobe output ready input inputs control signal that inserts wait states to bus cycle int input maskable interrupt request input pollb input synchronized sense signal input from external system nmi input non-maskable interrupt request input reset input system reset input clk input system clock input qs1, qs0 output queue status output buslockb 3-state output bus lock output bs2 to bs0 3-state output bus cycle status output miob 3-state output i/o access/memory access select output ps3 to ps0 output processor status output wrb 3-state output write strobe output intakb output interrupt acknowledge output astb output address strobe output bufrbw 3-state output buffer read/write output bufenb 3-state output buffer enable output hldrq input bus hold request input hldak output bus hold acknowledge output emsren input ems registers access enable input cnt2, cnt1 output 3-state output control output dc output d15 to d0 control output bunri input pin for test using test bus test input tbi27 to tbi0 input tbo71 to tbo0 3-state output ei3 to ei0 input nec reserved pin eo8 to eo0 output clko output chapter 5 v30mx 93 design manual a13195ej5v0dm 5. 5 electrical specifications the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 5. 5. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 5. 5. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 30 ns 5. 5. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit supply current i dd during normal operation 0.5 1.0 ma/mhz in standby (halt) mode 0.05 0.10 ma/mhz when clock is stopped 30 a chapter 5 v30mx 94 design manual a13195ej5v0dm 5. 5. 4 ac characteristics (t a = ? ? ? ? 40 to +85c, v dd = 3.3 v 0.3 v) (1) read timing (1/2) parameter symbol conditions min. max. unit clock cycle <1> t cyk 30 ns delay time from clk to address <2> t dka 2.4 11 ns delay time from clk to ubeb, buslockb <3> t dkub 2.4 11 ns delay time from clk to bs1, bs0 <4> t dkb 2.4 11 ns data setup time (to clk )<5>t sdk 3ns data hold time (from clk )<6>t hkd 6ns ready setup time (to clk )<7>t sryk 3ns ready hold time (from clk )<8>t hkry 3ns delay time from clk to astb <9> t dksth 1.3 6 ns delay time from clk to astb <10> t dkstl 1.3 5.5 ns delay time from clk to bufrbw <11> t dkct 1.9 9 ns delay time from bufrbw to bufenb <12> t rwen 02ns delay time from bufenb to bufrbw <13> t denrw 02ns delay time from clk to bufenb (read cycle) <14> t dkenr 1.9 9 ns delay time from clk to rdb , wrb <15> t dkcml 1.8 8.4 ns delay time from clk to rdb , wrb <16> t dkcmh 1.8 8.4 ns chapter 5 v30mx 95 design manual a13195ej5v0dm (1) read timing (2/2) clk (input) <2> <2> ts tc tc ts (next cycle) a23 to a0 (output) miob (output) bs2 (output) ubeb (output) buslockb (output) bs1, bs0 (output) d15 to d0 (i/o) ready (input) astb (output) bufrbw (output) bufenb (output) rdb (output) <1> <3> <3> <4> <4> <5> <6> <7> <8> <10> <9> <11> <13> <12> <15> <16> <14> hi-z hi-z input chapter 5 v30mx 96 design manual a13195ej5v0dm (2) write timing (1/2) parameter symbol conditions min. max. unit clock cycle <1> t cyk 30 ns delay time from clk to address <2> t dka 2.4 11 ns delay time from clk to ubeb, buslockb <3> t dkub 2.4 11 ns delay time from clk to bs1, bs0 <4> t dkb 2.4 11 ns ready setup time (to clk )<7>t sryk 3ns ready hold time (from clk )<8>t hkry 3ns delay time from clk to astb <9> t dksth 1.3 6 ns delay time from clk to astb <10> t dkstl 1.3 5.5 ns delay time from clk to rdb , wrb <15> t dkcml 1.8 8.4 ns delay time from clk to rdb , wrb <16> t dkcmh 1.8 8.4 ns delay time from clk to data float <17> t fkd 2.3 10 ns delay time from clk to bufenb (write cycle) <18> t dkenwh 1.4 7 ns delay time from clk to bufenb (write cycle) <19> t dkenwl 1.4 7 ns chapter 5 v30mx 97 design manual a13195ej5v0dm (2) write timing (2/2) clk (input) <2> <2> ts tc tc ts (next cycle) a23 to a0 (output) miob (output) bs2 (output) ubeb (output) buslockb (output) bs1, bs0 (output) d15 to d0 (i/o) ready (input) astb (output) bufrbw (output) bufenb (output) wrb (output) <1> <3> <3> <4> <4> <10> <15> <17> <4> <9> h <7> <8> <18> <19> <16> hi-z hi-z output chapter 5 v30mx 98 design manual a13195ej5v0dm (3) entering the bus hold status timing parameter symbol conditions min. max. unit delay time from clk to data float <17> t fkd 2.3 10 ns hldrq setup time (to clk) <20> t sik 3ns delay time from clk to hldak <21> t dkha 1.4 6 ns clk (input) tc tc ti th hldrq (input) hldak (output) a23 to a0 (output) miob (output) bs2 (output) ubeb (output) buslockb (output) bs1, bs0 (output) ready (input) astb (output) bufrbw (output) bufenb (output) wrb (output) ts th <20> <17> <17> <21> <17> <17> <17> <17> d15 to d0 (i/o) ti write operation bus hold status hi-z hi-z hi-z hi-z hi-z hi-z output chapter 5 v30mx 99 design manual a13195ej5v0dm (4) exiting the bus hold status timing parameter symbol conditions min. max. unit delay time from clk to address <2> t dka 2.4 11 ns delay time from clk to bs1, bs0 <4> t dkb 2.4 11 ns hldrq setup time (to clk) <20> t sik 3ns delay time from clk to hldak <21> t dkha 1.4 6 ns delay time from clk to data output <22> t dkd 2.2 10 ns clk (input) th th th ts th tc <22> <2> <2> bus hold status write operation <20> <21> <4> <2> hldrq (input) hldak (output) a23 to a0 (output) miob (output) bs2 (output) ubeb (output) buslockb (output) bs1, bs0 (output) ready (input) astb (output) bufrbw (output) bufenb (output) wrb (output) d15 to d0 (i/o) <2> hi-z hi-z hi-z hi-z hi-z hi-z hi-z chapter 5 v30mx 100 design manual a13195ej5v0dm (5) standby (halt) mode setup timing parameter symbol conditions min. max. unit delay time from clk to address <2> t dka 2.4 11 ns delay time from clk to ubeb, buslockb <3> t dkub 2.4 11 ns delay time from clk to bs1, bs0 <4> t dkb 2.4 11 ns delay time from clk to rdb , wrb <16> t dkcmh 1.8 8.4 ns delay time from clk to bufenb (write cycle) <19> t dkenwl 1.4 7 ns clk (input) ti ts ti ti tc <2> <3> <2> <2> <2> <4> <4> h <19> <16> ubeb (output) buslockb (output) bs2 (output) miob (output) bs1, bs0 (output) ready (input) astb (output) bufrbw (output) bufenb (output) rdb (output) wrb (output) d15 to d0 (i/o) a23 to a0 (output) hi-z chapter 5 v30mx 101 design manual a13195ej5v0dm (6) interrupt acknowledge timing parameter symbol conditions min. max. unit delay time from clk to intakb <23> t dkif 1.4 7 ns delay time from clk to intakb <24> t dkir 1.4 7 ns clk (input) tc ts tc tc ti ti ti ts tc tc ti <23> <24> <23> <24> bs1, bs0 (output) miob (output) bs2 (output) buslockb (output) a23 to a0 (output) ubeb (output) d15 to d0 (i/o) ready (input) intakb (output) astb (output) rdb (output) bufrbw (output) bufenb (output) interrupt vector number ts second interrupt cycle first interrupt cycle hi-z hi-z chapter 5 v30mx 102 design manual a13195ej5v0dm (7) reset, int, nmi, hldrq input timing parameter symbol conditions min. max. unit asynchronous signals note setup time (to clk) <20> t sik 3ns asynchronous signals note hold time (from clk) <25> t hik 6ns note asynchronous signals: reset, int, nmi, hldrq (8) clk input timing parameter symbol conditions min. max. unit clock high-level width <26> t kkh 10 ns clock low-level width <27> t kkl 10 ns (9) reset timing parameter symbol conditions min. max. unit reset high-level width <28> t wrsth 4t cyk ns clk (input) hldrq (input) reset (input) int (input) nmi (input) <20> <25> <20> <25> clk (input) <26> <27> reset (input) <28> 103 design manual a13195ej5v0dm chapter 6 V30MZ (under development) the V30MZ is a cpu core that has further improved the cpu core ?v30mx?, which has increased bus efficiency of the nec original microprocessor ? pd70116h? (commonly known as v30hl). high-speed processing at the speed of a risc microprocessor has been made possible due to the raising of bus efficiency with the realization of a 1 clock/1 bus cycle, and the considerable increase in instruction execution speed through internal pipelining. compared to the 4.3 mips (at 33 mhz operation, no wait) of the v30mx, the V30MZ has realized a processing performance of 35 mips (at 66 mhz operation, no wait). 6. 1 outline ? processing performance: 35mips (@ 66 mhz operation, no wait) ? cmos static design (capable of complete stop of the internal system clock) ? 1 clock/1 bus cycle ? external bus interface address bus: 20 bits data bus: 16 bits (i/o separate buses) ? bus hold function ? standby function (halt mode) chapter 6 V30MZ 104 design manual a13195ej5v0dm 6. 1. 1 symbol diagram number of grids 207k grids 251k grids (including wiring area) number of separation simulation patterns 52k 6. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) clk 0.012 1.912 di15 to di0 0.012 1.912 reset 0.012 1.912 bunri 0.037 1.937 nmi 0.012 1.912 test 0.010 1.910 int 0.012 1.912 tbi22 to tbi0 0.011 1.911 hldrq 0.012 1.912 dbint 0.008 1.908 pollb 0.012 1.912 dbnmim 0.008 1.908 readyb 0.012 1.912 ubeb bs (3:0) do (15:0) di (15:0) a (19:0) out hldak nmi int clk tbo (42:0) tbi (22:0) test bunri in in in out hldrq pollb reset buslockb dbint dbmode dba20 dbrd dbwr dbnmim dbhltst teoi tilen (3:0) tbra tinta out out out out out out out out out out out out out in in in in in in in in in readyb in out chapter 6 V30MZ 105 design manual a13195ej5v0dm (2) output pins pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) a19 to a0 13.072 ?? dba20 13.072 ?? bs3 to bs0 13.072 ?? dbrd 13.072 ?? do15 to do0 13.072 ?? dbwr 13.072 ?? buslockb 13.072 ?? dbhltst 13.072 ?? hldak 13.072 ?? teoi 13.072 ?? ubeb 13.072 ?? tilen3 to tilen0 13.072 ?? tbo42 to tbo0 6.536 0.047 1.947 tbra 13.072 ?? dbmode 13.072 ?? tinta 13.072 ?? 6. 2 notes for simulation execution 6. 2. 1 notes for v.sim simulation when simulation is executed through v.sim, input the following command. command>mr instance-name/_ntmzrom ntmzrom ntmzrom.nincf 6. 2. 2 timing verification input timing verification methods vary depending on the simulator used. for verilog-xl, input timing verification is performed at execution, but for v.sim, no error message is output even if the input error ocurred at execution. for v.sim, be sure to verify by executing the opencad menu ?megamacro timing check?. if other simulators are used, contact nec for verification methods. chapter 6 V30MZ 106 design manual a13195ej5v0dm 6. 3 notes for initialization 6. 3. 1 reset signal the reset signal is executed from an instruction in the ffff0h address after the high levels of at least four clocks have been input to the reset pin, and upon the release of the reset following the input of the low levels. be aware that if the variable timing of the reset signal conflicts with the clock rise, a timing error will be generated and the reset operation may not run normally. the reset input must be set to low level when the reset is released. figure 6-1. reset signal input example 6. 3. 2 clk input a cpu reset occurs only when the clk input toggles. care should be taken when a frequency divider is inserted at the clk input of the cpu. (1) correct (2) incorrect r q t source clock clk reset system reset frequency d ivider reset r q t source clock clk reset system reset a system reset occurs, after the frequency division period reset is released. with this circuit, no reset can occur. 6. 3. 3 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in test program execution. clk (input) reset (input) reset period reset released chapter 6 V30MZ 107 design manual a13195ej5v0dm 6. 4 pin functions pin name i/o function a19 to a0 output address output di15 to di0 input data input do15 to do0 output data output ubeb output upper byte enable signal output of data bus bs3 to bs0 output bus cycle status output readyb input inputs control signal that inserts wait states to bus cycle buslockb output bus lock output pollb input synchronized sense signal input from external system reset input system reset input hldrq input bus hold request input hldak output bus hold acknowledge output nmi input non-maskable interrupt request input int input maskable interrupt request input clk input system clock input bunri input pin for test using test bus test input tbi22 to tbi0 input tbo42 to tbo0 output dbint input nec reserved pin dbmode output dba20 output dbrd output dbwr output dbnmim input dbhltst output teoi output tilen3 to tilen0 output tbra output tinta output chapter 6 V30MZ 108 design manual a13195ej5v0dm 6. 5 electrical specifications (preliminary) the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 6. 5. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 6. 5. 2 recommended operation range parameter symbol conditions min. typ. max. unit supply voltage v dd at 2.0 v supply voltage 1.8 2.0 2.2 v at 3.3 v supply voltage 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c at 2.0 v supply voltage 31 ns clock cycle t cyk at 3.3 v supply voltage 15 ns 6. 5. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c) (1) at 2.0 v supply voltage (v dd = 2.0 v 0.2 v) parameter symbol conditions min. typ. max. unit i dd during operation 0.4 0.8 ma/mhz in halt mode 2 4 a/mhz supply current when clock is stopped 0 a (2) at 3.3 v supply voltage (v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd during operation 0.6 1.2 ma/mhz in halt mode 5 10 a/mhz supply current when clock is stopped 0 a chapter 6 V30MZ 109 design manual a13195ej5v0dm 6. 5. 4 ac characteristics (t a = ? ? ? ? 40 to +85c) (1) clk input timing (a) at 2.0 v supply voltage (v dd = 2.0 v 0.2 v) parameter symbol conditions min. max. unit operating frequency 32 mhz clock cycle <1> t cyk 31 ns clock high-level width <2> t kkh 15.5 ns clock low-level width <3> t kkl 15.5 ns (b) at 3.3 v supply voltage (v dd = 3.3 v 0.3 v) parameter symbol conditions min. max. unit operating frequency 66 mhz clock cycle <1> t cyk 15 ns clock high-level width <2> t kkh 7ns clock low-level width <3> t kkl 7ns clk (input) <1> <2> <3> chapter 6 V30MZ 110 design manual a13195ej5v0dm (2) reset, int, nmi, hldrq, pollb input timing (a) at 2.0 v supply voltage (v dd = 2.0 v 0.2 v) parameter symbol conditions min. max. unit asynchronous signals note setup time <4> t sik 2ns asynchronous signals note hold time <5> t hki 2ns pollb setup time <6> t spk 2ns pollb hold time <7> t hkp 6ns note asynchronous signals: reset, int, nmi, hldrq (b) at 3.3 v supply voltage (v dd = 3.3 v 0.3 v) parameter symbol conditions min. max. unit asynchronous signals note setup time <4> t sik 2ns asynchronous signals note hold time <5> t hki 2ns pollb setup time <6> t spk 2ns pollb hold time <7> t hkp 4ns note asynchronous signals: reset, int, nmi, hldrq <5> <4> clk (input) reset (input) int (input) nmi (input) hldrq (input) <7> pollb (input) <6> 111 design manual a13195ej5v0dm [memo] chapter 6 V30MZ 112 design manual a13195ej5v0dm (3) timings of signals related to bus cycle (1/2) (a) at 2.0 v supply voltage (v dd = 2.0 v 0.2 v) parameter symbol conditions min. max. unit address bus output delay time <8> t dka 110ns bus status output delay time <9> t dkb 110ns data output delay time <10> t dkd 215ns buslockb delay time <11> t dkbl 110ns hldak delay time <12> t dkha 110ns data input setup time <13> t sdk 2ns data input hold time <14> t hkd 6ns readyb setup time <15> t srk 7ns readyb hold time <16> t hkr 4ns (b) at 3.3 v supply voltage (v dd = 3.3 v 0.3 v) parameter symbol conditions min. max. unit address bus output delay time <8> t dka 15ns bus status output delay time <9> t dkb 15ns data output delay time <10> t dkd 27.5ns buslockb delay time <11> t dkbl 15ns hldak delay time <12> t dkha 0.5 5 ns data input setup time <13> t sdk 1ns data input hold time <14> t hkd 3ns readyb setup time <15> t srk 3ns readyb hold time <16> t hkr 2ns chapter 6 V30MZ 113 design manual a13195ej5v0dm (3) timings of signals related to bus cycle (2/2) <13> clk (input) <8> a19 to a0 (output) ubeb (output) <9> bs3 to bs0 (output) do15 to do0 (output) <10> buslockb (output) <11> hldak (output) <12> di15 to di0 (input) <14> <15> readyb (input) <16> 114 design manual a13195ej5v0dm chapter 7 nb85e (under development) the nb85e is a cpu core provided for incorporation in asics and includes on chip the ?v850e1? cpu, nec?s 32- bit risc microprocessor, as well as various peripheral i/o functions such as dma and interrupt controllers. 7. 1 outline ? processing performance: 82 mips (@ 66 mhz operation) ? memory space program area: 64 mb linear data area: 4 gb linear memory bank division function: 2, 4, and 8 mb/bank ? minimum instruction execution time: 15 ns (@ 66 mhz operation) ? external bus interface vsb (v850e system bus) npb (nec peripheral i/o bus) ? interrupt/exception control function non-maskable interrupts: 3 sources maskable interrupts: 64 sources exceptions: 1 source 8 priority levels specifiable (maskable interrupts) ? dma control function 4-channel structure transfer unit: 8, 16, and 32 bits maximum number of transfers: 65536 (2 16 ) transfer type: flyby (1-cycle) transfer, 2-cycle transfer transfer mode: single transfer, single step transfer, line transfer, block transfer terminal count output signals (dmtco3 to dmtco0) ? power save function halt, hardware/software stop modes ? nb85e901 (rcu note ) interface function note rcu (run control unit): a control unit for executing jtag communication or debug processing. chapter 7 nb85e 115 design manual a13195ej5v0dm 7. 1. 1 symbol diagram number of grids 351.6k grids 574.4k grids (including wiring area) number of separation simulation patterns 194.7k chapter 7 nb85e 116 design manual a13195ej5v0dm evirel in vaack vareq idmastp in dmarq (3:0) in dmtco (3:0) out dmactv (3:0) out ibdrrq ibea (25:2) ibaack ibdrdy ibdle 3:0) ibedi (31:0) ibbtft iidrrq iiea (25:2) iiaack iidlef iiedi (31:0) iibtft iircan bcunch vptclk out phtest out tesen out tbo (34:0) out cgrel swstoprq hwstoprq dcstopz stprq stpak tbredz out out vpa (13:0) in/out vpd (15:0) out vpwrite out vpstb out out in in vplock vpubenz vpretr vpdact vdselpz vdcsz (7:0) vbseq (2:0) vbctyp (2:0) vbsize (1:0) vbbenz (3:0) vbttyp (1:0) vbd (31:0) in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out out in/out in/out vba (27:0) vbstz vbwrite vblock vbbstr vbwait vblast vbahld vbdc dcresz vbclk test in bunri in out phtdin (1:0) in phtdo (1:0) iroma (19:2) out iromz (31:0) in iromen out iromcs out iromia out iromae out iromwt in irama (27:2) out iramz (31:0) in iramen out iramwr (3:0) out iramrwb out iraoz (31:0) out iramwt in out tmode (1:0) tbi (39:0) in int (63:0) dcnmi (2:0) in in vpresz out iddarq iddrrq iddwrq idaack idseq2 idseq4 irrsa idretr ides iddrdy idrrdy idhum idea (27:0) ided (31:0) idunch out in in out in in out out out out out in in in in/out dbi (5:0) dbo (14:0) dbb (15:0) evastb evdstb evad (15:0) evlkrt evclrip evintak evintrq evintlv (6:0) evien evoen in in in/out out out in/out in in out out ifinsz (1:0) ifirome ifirob2 ifirobe ifiropr ifimode2 ifira16 ifira32 ifira64 ifirase ifirabe ifiuswe ifimaen ifid256 ifiunch (1:0) fcomb pheva ifiwrth ifimode3 in in in in in in in in in in in in in in in in in in in in out in/out out out out out in in in in in in out out out out out out in in in out out out in in in ( chapter 7 nb85e 117 design manual a13195ej5v0dm 7. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins (1/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) vpretr 0.746 2.646 int45 0.029 1.929 vpdact 0.297 2.197 int44 0.014 1.914 vareq 0.175 2.075 int43 0.017 1.917 dcresz 0.166 2.066 int42 0.041 1.941 vbclk 0.480 2.380 int41 0.014 1.914 cgrel 0.204 2.104 int40 0.021 1.921 dcstopz 0.260 2.160 int39 0.018 1.918 stpak 0.230 2.130 int38 0.011 1.911 idmastp 0.178 2.078 int37 0.008 1.908 dmarq3 0.180 2.080 int36 0.007 1.907 dmarq2 0.189 2.089 int35 0.009 1.909 dmarq1 0.153 2.053 int34 0.032 1.932 dmarq0 0.177 2.077 int33 0.068 1.968 dcnmi2 0.021 1.921 int32 0.016 1.916 dcnmi1 0.015 1.915 int31 0.012 1.912 dcnmi0 0.010 1.910 int30 0.016 1.916 int63 0.020 1.920 int29 0.018 1.918 int62 0.014 1.914 int28 0.016 1.916 int61 0.014 1.914 int27 0.013 1.913 int60 0.014 1.914 int26 0.010 1.910 int59 0.035 1.935 int25 0.011 1.911 int58 0.023 1.923 int24 0.024 1.924 int57 0.011 1.911 int23 0.023 1.923 int56 0.029 1.929 int22 0.023 1.923 int55 0.008 1.908 int21 0.016 1.916 int54 0.011 1.911 int20 0.028 1.928 int53 0.014 1.914 int19 0.014 1.914 int52 0.041 1.941 int18 0.009 1.909 int51 0.029 1.929 int17 0.008 1.908 int50 0.019 1.919 int16 0.039 1.939 int49 0.041 1.941 int15 0.007 1.907 int48 0.011 1.911 int14 0.026 1.926 int47 0.022 1.922 int13 0.022 1.922 int46 0.027 1.927 int12 0.026 1.926 chapter 7 nb85e 118 design manual a13195ej5v0dm (1) input pins (2/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) int11 0.061 1.961 iromz4 0.726 2.626 int10 0.051 1.951 iromz3 0.848 2.748 int9 0.028 1.928 iromz2 0.731 2.631 int8 0.025 1.925 iromz1 0.581 2.481 int7 0.013 1.913 iromz0 0.717 2.617 int6 0.027 1.927 iromwt 0.070 1.970 int5 0.023 1.923 iramz31 0.274 2.174 int4 0.018 1.918 iramz30 0.159 2.059 int3 0.012 1.912 iramz29 0.255 2.155 int2 0.022 1.922 iramz28 0.298 2.198 int1 0.030 1.930 iramz27 0.280 2.180 int0 0.012 1.912 iramz26 0.275 2.175 iromz31 0.673 2.573 iramz25 0.200 2.100 iromz30 1.383 3.283 iramz24 0.281 2.181 iromz29 1.122 3.022 iramz23 0.207 2.107 iromz28 0.754 2.654 iramz22 0.189 2.089 iromz27 0.695 2.595 iramz21 0.320 2.220 iromz26 1.017 2.917 iramz20 0.290 2.190 iromz25 1.267 3.167 iramz19 0.415 2.315 iromz24 1.203 3.103 iramz18 0.295 2.195 iromz23 1.381 3.281 iramz17 0.389 2.289 iromz22 0.860 2.760 iramz16 0.322 2.222 iromz21 0.645 2.545 iramz15 0.234 2.134 iromz20 1.473 3.373 iramz14 0.202 2.102 iromz19 0.738 2.638 iramz13 0.289 2.189 iromz18 0.751 2.651 iramz12 0.296 2.196 iromz17 0.631 2.531 iramz11 0.317 2.217 iromz16 0.653 2.553 iramz10 0.254 2.154 iromz15 0.805 2.705 iramz9 0.320 2.220 iromz14 0.662 2.562 iramz8 0.344 2.244 iromz13 0.783 2.683 iramz7 0.305 2.205 iromz12 0.757 2.657 iramz6 0.225 2.125 iromz11 0.855 2.755 iramz5 0.317 2.217 iromz10 0.712 2.612 iramz4 0.495 2.395 iromz9 0.686 2.586 iramz3 0.542 2.442 iromz8 0.769 2.669 iramz2 0.418 2.318 iromz7 0.781 2.681 iramz1 0.264 2.164 iromz6 0.775 2.675 iramz0 0.289 2.189 iromz5 0.635 2.535 iramwt 0.463 2.363 chapter 7 nb85e 119 design manual a13195ej5v0dm (1) input pins (3/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) ibdrrq 0.166 2.066 iiedi19 0.054 1.954 ibea25 0.153 2.053 iiedi18 0.067 1.967 ibea24 0.050 1.950 iiedi17 0.058 1.958 ibea23 0.141 2.041 iiedi16 0.017 1.917 ibea22 0.171 2.071 iiedi15 0.074 1.974 ibea21 0.169 2.069 iiedi14 0.055 1.955 ibea20 0.196 2.096 iiedi13 0.059 1.959 ibea19 0.040 1.940 iiedi12 0.074 1.974 ibea18 0.101 2.001 iiedi11 0.051 1.951 ibea17 0.105 2.005 iiedi10 0.066 1.966 ibea16 0.129 2.029 iiedi9 0.071 1.971 ibea15 0.059 1.959 iiedi8 0.059 1.959 ibea14 0.082 1.982 iiedi7 0.034 1.934 ibea13 0.084 1.984 iiedi6 0.057 1.957 ibea12 0.058 1.958 iiedi5 0.068 1.968 ibea11 0.018 1.918 iiedi4 0.061 1.961 ibea10 0.114 2.014 iiedi3 0.073 1.973 ibea9 0.066 1.966 iiedi2 0.060 1.960 ibea8 0.131 2.031 iiedi1 0.085 1.985 ibea7 0.061 1.961 iiedi0 0.088 1.988 ibea6 0.041 1.941 ibbtft 0.189 2.089 ibea5 0.040 1.940 iddrrq 0.444 2.344 ibea4 0.045 1.945 iddwrq 0.287 2.187 ibea3 0.170 2.070 idseq4 0.177 2.077 ibea2 0.180 2.080 idseq2 0.570 2.470 iiaack 0.186 2.086 idrrdy 0.495 2.395 iidlef 0.073 1.973 idhum 0.329 2.229 iiedi31 0.062 1.962 idea27 0.425 2.325 iiedi30 0.056 1.956 idea26 0.474 2.374 iiedi29 0.103 2.003 idea25 0.401 2.301 iiedi28 0.067 1.967 idea24 0.382 2.282 iiedi27 0.053 1.953 idea23 0.345 2.245 iiedi26 0.055 1.955 idea22 0.346 2.246 iiedi25 0.077 1.977 idea21 0.399 2.299 iiedi24 0.016 1.916 idea20 0.414 2.314 iiedi23 0.064 1.964 idea19 0.283 2.183 iiedi22 0.063 1.963 idea18 0.298 2.198 iiedi21 0.065 1.965 idea17 0.303 2.203 iiedi20 0.064 1.964 idea16 0.292 2.192 chapter 7 nb85e 120 design manual a13195ej5v0dm (1) input pins (4/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) idea15 0.292 2.192 pheva 1.468 3.368 idea14 0.292 2.192 ifirobe 0.470 2.370 idea13 0.270 2.170 ifiropr 0.424 2.324 idea12 0.289 2.189 ifirase 0.715 2.615 idea11 0.277 2.177 ifirabe 0.923 2.823 idea10 0.313 2.213 ifimode3 0.478 2.378 idea9 0.244 2.144 ifimode2 0.557 2.457 idea8 0.269 2.169 ifiuswe 0.277 2.177 idea7 0.270 2.170 fcomb 0.284 2.184 idea6 0.249 2.149 tbi39 0.022 1.922 idea5 0.273 2.173 tbi38 0.008 1.908 idea4 0.268 2.168 tbi37 0.009 1.909 idea3 0.290 2.190 tbi36 0.137 2.037 idea2 0.276 2.176 tbi35 0.497 2.397 idea1 0.331 2.231 tbi34 0.007 1.907 idea0 0.386 2.286 tbi33 0.146 2.046 dbi5 0.199 2.099 tbi32 0.134 2.034 dbi4 0.296 2.196 tbi31 0.011 1.911 dbi3 0.530 2.430 tbi30 0.012 1.912 dbi2 0.413 2.313 tbi29 0.009 1.909 dbi1 0.543 2.443 tbi28 0.009 1.909 dbi0 0.691 2.591 tbi27 0.011 1.911 evastb 0.459 2.359 tbi26 0.011 1.911 evdstb 0.091 1.991 tbi25 0.010 1.910 evirel 0.274 2.174 tbi24 0.009 1.909 evclrip 0.035 1.935 tbi23 0.013 1.913 evintak 0.150 2.050 tbi22 0.016 1.916 ifirome 0.281 2.181 tbi21 0.011 1.911 ifirob2 0.292 2.192 tbi20 0.051 1.951 ifira64 0.596 2.496 tbi19 0.043 1.943 ifira32 0.524 2.424 tbi18 0.169 2.069 ifira16 0.441 2.341 tbi17 0.035 1.935 ifimaen 0.363 2.263 tbi16 0.022 1.922 ifid256 0.424 2.324 tbi15 0.020 1.920 ifinsz1 0.405 2.305 tbi14 0.017 1.917 ifinsz0 0.573 2.473 tbi13 0.011 1.911 ifiwrth 0.377 2.277 tbi12 0.039 1.939 ifiunch1 0.694 2.594 tbi11 0.035 1.935 ifiunch0 0.709 2.609 tbi10 0.027 1.927 chapter 7 nb85e 121 design manual a13195ej5v0dm (1) input pins (5/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) tbi9 0.019 1.919 tbi2 0.007 1.907 tbi8 0.025 1.925 tbi1 0.008 1.908 tbi7 0.012 1.912 tbi0 0.013 1.913 tbi6 0.024 1.924 test 0.018 1.918 tbi5 0.045 1.945 bunri 0.371 2.271 tbi4 0.030 1.930 phtdo1 0.535 2.435 tbi3 0.007 1.907 phtdo0 0.535 2.435 (2) output pins (1/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vpa13 3.250 ?? dmactv2 3.168 ?? vpa12 3.243 ?? dmactv1 3.006 ?? vpa11 3.243 ?? dmactv0 2.949 ?? vpa10 3.239 ?? iroma19 13.008 ?? vpa9 3.234 ?? iroma18 3.191 ?? vpa8 3.245 ?? iroma17 3.177 ?? vpa7 3.238 ?? iroma16 3.195 ?? vpa6 3.241 ?? iroma15 3.079 ?? vpa5 3.239 ?? iroma14 3.177 ?? vpa4 3.228 ?? iroma13 3.168 ?? vpa3 3.294 ?? iroma12 3.189 ?? vpa2 3.293 ?? iroma11 3.186 ?? vpa1 3.292 ?? iroma10 3.092 ?? vpa0 3.211 ?? iroma9 3.095 ?? vpwrite 3.176 ?? iroma8 13.001 ?? vpstb 3.174 ?? iroma7 3.102 ?? vplock 3.254 ?? iroma6 6.532 ?? vpubenz 3.294 ?? iroma5 6.536 ?? vaack 13.316 ?? iroma4 6.564 ?? vbdc 13.021 ?? iroma3 6.525 ?? swstoprq 4.630 ?? iroma2 6.531 ?? hwstoprq 12.809 ?? iromen 12.912 ?? stprq 4.578 ?? iromcs 4.754 ?? dmtco3 3.159 ?? iromia 6.503 ?? dmtco2 3.180 ?? iromae 12.933 ?? dmtco1 3.141 ?? irama27 3.040 ?? dmtco0 3.135 ?? irama26 3.246 ?? dmactv3 3.044 ?? irama25 3.273 ?? chapter 7 nb85e 122 design manual a13195ej5v0dm (2) output pins (2/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) irama24 3.020 ?? iraoz15 3.159 ?? irama23 3.030 ?? iraoz14 3.362 ?? irama22 3.241 ?? iraoz13 3.360 ?? irama21 3.032 ?? iraoz12 3.351 ?? irama20 3.049 ?? iraoz11 3.354 ?? irama19 3.298 ?? iraoz10 3.349 ?? irama18 2.969 ?? iraoz9 3.055 ?? irama17 3.293 ?? iraoz8 3.155 ?? irama16 3.256 ?? iraoz7 3.295 ?? irama15 3.292 ?? iraoz6 3.293 ?? irama14 3.279 ?? iraoz5 3.290 ?? irama13 3.290 ?? iraoz4 3.289 ?? irama12 3.292 ?? iraoz3 3.296 ?? irama11 4.957 ?? iraoz2 3.339 ?? irama10 3.291 ?? iraoz1 3.134 ?? irama9 3.179 ?? iraoz0 3.333 ?? irama8 3.290 ?? iramen 3.292 ?? irama7 3.176 ?? iramwr3 3.284 ?? irama6 3.292 ?? iramwr2 3.288 ?? irama5 3.256 ?? iramwr1 13.068 ?? irama4 3.273 ?? iramwr0 3.287 ?? irama3 13.067 ?? iramrwb 3.288 ?? irama2 3.287 ?? ibaack 3.296 ?? iraoz31 3.061 ?? ibdrdy 3.293 ?? iraoz30 3.360 ?? ibdle3 12.933 ?? iraoz29 3.359 ?? ibdle2 4.799 ?? iraoz28 3.360 ?? ibdle1 4.803 ?? iraoz27 3.350 ?? ibdle0 4.679 ?? iraoz26 3.352 ?? ibedi31 3.292 ?? iraoz25 3.211 ?? ibedi30 3.293 ?? iraoz24 3.353 ?? ibedi29 3.270 ?? iraoz23 3.357 ?? ibedi28 3.285 ?? iraoz22 2.998 ?? ibedi27 3.294 ?? iraoz21 3.345 ?? ibedi26 3.290 ?? iraoz20 3.151 ?? ibedi25 3.287 ?? iraoz19 3.347 ?? ibedi24 3.292 ?? iraoz18 3.170 ?? ibedi23 3.294 ?? iraoz17 3.362 ?? ibedi22 3.289 ?? iraoz16 3.362 ?? ibedi21 3.288 ?? chapter 7 nb85e 123 design manual a13195ej5v0dm (2) output pins (3/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) ibedi20 3.295 ?? iiea8 4.874 ?? ibedi19 3.295 ?? iiea7 13.046 ?? ibedi18 3.291 ?? iiea6 13.066 ?? ibedi17 3.293 ?? iiea5 13.068 ?? ibedi16 3.294 ?? iiea4 13.055 ?? ibedi15 3.292 ?? iiea3 12.956 ?? ibedi14 3.292 ?? iiea2 12.956 ?? ibedi13 3.290 ?? iibtft 3.242 ?? ibedi12 3.289 ?? iircan 3.292 ?? ibedi11 3.293 ?? bcunch 12.990 ?? ibedi10 3.286 ?? iddarq 3.214 ?? ibedi9 3.286 ?? idaack 2.990 ?? ibedi8 3.280 ?? irrsa 13.001 ?? ibedi7 3.283 ?? idretr 9.004 ?? ibedi6 3.288 ?? idunch 3.286 ?? ibedi5 3.290 ?? iddrdy 12.877 ?? ibedi4 3.289 ?? ides 12.836 ?? ibedi3 3.282 ?? dbo14 7.685 ?? ibedi2 3.289 ?? dbo13 2.793 ?? ibedi1 3.285 ?? dbo12 2.868 ?? ibedi0 3.287 ?? dbo11 3.105 ?? iidrrq 12.951 ?? dbo10 2.700 ?? iiea25 12.929 ?? dbo9 2.745 ?? iiea24 4.989 ?? dbo8 2.813 ?? iiea23 4.982 ?? dbo7 2.882 ?? iiea22 4.857 ?? dbo6 2.877 ?? iiea21 4.951 ?? dbo5 2.883 ?? iiea20 4.953 ?? dbo4 2.761 ?? iiea19 6.533 ?? dbo3 12.566 ?? iiea18 4.911 ?? dbo2 12.614 ?? iiea17 6.529 ?? dbo1 2.777 ?? iiea16 12.996 ?? dbo0 2.894 ?? iiea15 13.040 ?? evien 3.261 ?? iiea14 13.060 ?? evoen 4.988 ?? iiea13 13.038 ?? evintrq 4.675 ?? iiea12 4.945 ?? evintlv6 12.810 ?? iiea11 13.067 ?? evintlv5 12.708 ?? iiea10 12.966 ?? evintlv4 12.760 ?? iiea9 13.066 ?? evintlv3 12.708 ?? chapter 7 nb85e 124 design manual a13195ej5v0dm (2) output pins (4/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) evintlv2 6.212 ?? tbo13 6.511 0.071 1.971 evintlv1 12.687 ?? tbo12 6.513 0.069 1.969 evintlv0 12.683 ?? tbo11 6.524 0.059 1.959 tbo34 4.959 0.036 1.936 tbo10 6.516 0.067 1.967 tbo33 4.950 0.045 1.945 tbo9 6.501 0.081 1.981 tbo32 4.932 0.063 1.963 tbo8 6.511 0.072 1.972 tbo31 4.864 0.131 2.031 tbo7 6.507 0.075 1.975 tbo30 4.672 0.323 2.223 tbo6 6.527 0.055 1.955 tbo29 4.780 0.215 2.115 tbo5 6.532 0.050 1.950 tbo28 4.889 0.106 2.006 tbo4 6.502 0.080 1.980 tbo27 6.343 0.239 2.139 tbo3 6.528 0.054 1.954 tbo26 6.503 0.080 1.980 tbo2 6.509 0.073 1.973 tbo25 6.257 0.325 2.225 tbo1 6.519 0.063 1.963 tbo24 6.469 0.113 2.013 tbo0 6.518 0.065 1.965 tbo23 6.488 0.094 1.994 tesen 3.174 ?? tbo22 6.462 0.121 2.021 vptclk 3.250 ?? tbo21 6.445 0.137 2.037 phtdin1 3.288 ?? tbo20 6.500 0.083 1.983 phtdin0 3.290 ?? tbo19 6.515 0.067 1.967 vpresz 4.731 ?? tbo18 6.441 0.141 2.041 phtest 12.785 ?? tbo17 6.485 0.097 1.997 tmode1 2.483 ?? tbo16 6.506 0.076 1.976 tmode0 2.758 ?? tbo15 4.937 0.058 1.958 tbredz 3.113 ?? tbo14 6.480 0.103 2.003 (3) i/o pins (1/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vpd15 5.962 0.620 2.520 vpd4 5.962 0.620 2.520 vpd14 5.897 0.686 2.586 vpd3 5.936 0.646 2.546 vpd13 5.843 0.740 2.640 vpd2 5.908 0.675 2.575 vpd12 5.846 0.736 2.636 vpd1 5.906 0.676 2.576 vpd11 5.907 0.675 2.575 vpd0 5.912 0.670 2.570 vpd10 5.921 0.661 2.561 vba27 4.343 0.652 2.552 vpd9 5.902 0.680 2.580 vba26 4.252 0.743 2.643 vpd8 5.910 0.672 2.572 vba25 2.661 0.678 2.578 vpd7 5.946 0.636 2.536 vba24 4.336 0.659 2.559 vpd6 5.954 0.629 2.529 vba23 4.352 0.643 2.543 vpd5 5.922 0.661 2.561 vba22 4.302 0.693 2.593 chapter 7 nb85e 125 design manual a13195ej5v0dm (3) i/o pins (2/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vba21 4.316 0.679 2.579 vbd14 3.469 1.525 3.425 vba20 4.307 0.687 2.587 vbd13 3.563 1.432 3.332 vba19 4.304 0.691 2.591 vbd12 3.537 1.458 3.358 vba18 4.236 0.758 2.658 vbd11 3.500 1.494 3.394 vba17 4.195 0.800 2.700 vbd10 3.444 1.551 3.451 vba16 2.614 0.724 2.624 vbd9 3.596 1.399 3.299 vba15 4.235 0.760 2.660 vbd8 3.389 1.606 3.506 vba14 4.291 0.704 2.604 vbd7 3.267 1.728 3.628 vba13 4.201 0.794 2.694 vbd6 3.133 1.862 3.762 vba12 4.181 0.814 2.714 vbd5 3.250 1.745 3.645 vba11 4.201 0.794 2.694 vbd4 3.205 1.790 3.690 vba10 4.196 0.799 2.699 vbd3 3.186 1.808 3.708 vba9 4.220 0.775 2.675 vbd2 3.173 1.822 3.722 vba8 4.229 0.766 2.666 vbd1 3.211 1.784 3.684 vba7 4.174 0.821 2.721 vbd0 3.215 1.780 3.680 vba6 4.186 0.809 2.709 vbttyp1 5.827 0.756 2.656 vba5 4.255 0.740 2.640 vbttyp0 5.809 0.773 2.673 vba4 4.219 0.776 2.676 vbstz 2.596 0.742 2.642 vba3 4.191 0.804 2.704 vbbenz3 5.737 0.845 2.745 vba2 4.212 0.783 2.683 vbbenz2 5.783 0.799 2.699 vba1 4.179 0.816 2.716 vbbenz1 5.689 0.894 2.794 vba0 4.161 0.834 2.734 vbbenz0 5.599 0.983 2.883 vbd31 3.720 1.275 3.175 vbsize1 4.081 0.914 2.814 vbd30 3.419 1.576 3.476 vbsize0 4.208 0.787 2.687 vbd29 3.733 1.262 3.162 vbwrite 2.543 0.796 2.696 vbd28 3.690 1.304 3.204 vblock 4.130 0.865 2.765 vbd27 3.823 1.172 3.072 vbctyp2 4.176 0.819 2.719 vbd26 3.651 1.344 3.244 vbctyp1 2.612 0.727 2.627 vbd25 3.760 1.235 3.135 vbctyp0 2.564 0.775 2.675 vbd24 3.737 1.258 3.158 vbseq2 4.204 0.791 2.691 vbd23 3.724 1.271 3.171 vbseq1 4.174 0.821 2.721 vbd22 3.706 1.289 3.189 vbseq0 4.199 0.796 2.696 vbd21 3.699 1.296 3.196 vbbstr 2.595 0.744 2.644 vbd20 3.705 1.290 3.190 vbwait 5.742 0.840 2.740 vbd19 3.751 1.244 3.144 vblast 5.785 0.797 2.697 vbd18 3.668 1.327 3.227 vbahld 5.811 0.771 2.671 vbd17 3.741 1.254 3.154 vdcsz7 4.336 0.659 2.559 vbd16 3.617 1.377 3.277 vdcsz6 4.347 0.648 2.548 vbd15 3.458 1.537 3.437 vdcsz5 4.344 0.651 2.551 chapter 7 nb85e 126 design manual a13195ej5v0dm (3) i/o pins (3/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vdcsz4 4.291 0.704 2.604 ided1 5.912 0.670 2.570 vdcsz3 4.369 0.626 2.526 ided0 5.895 0.688 2.588 vdcsz2 4.336 0.659 2.559 dbb15 4.055 0.940 2.840 vdcsz1 4.357 0.637 2.537 dbb14 4.023 0.972 2.872 vdcsz0 4.347 0.648 2.548 dbb13 4.031 0.964 2.864 vdselpz 4.180 0.815 2.715 dbb12 4.012 0.983 2.883 ided31 5.749 0.833 2.733 dbb11 3.993 1.002 2.902 ided30 4.419 0.576 2.476 dbb10 3.999 0.996 2.896 ided29 5.798 0.785 2.685 dbb9 3.971 1.024 2.924 ided28 5.798 0.784 2.684 dbb8 4.019 0.976 2.876 ided27 4.424 0.571 2.471 dbb7 4.012 0.982 2.882 ided26 5.819 0.763 2.663 dbb6 4.028 0.967 2.867 ided25 5.809 0.774 2.674 dbb5 3.949 1.046 2.946 ided24 5.767 0.815 2.715 dbb4 4.002 0.993 2.893 ided23 5.726 0.856 2.756 dbb3 3.863 1.131 3.031 ided22 5.764 0.818 2.718 dbb2 3.952 1.043 2.943 ided21 5.833 0.750 2.650 dbb1 4.051 0.944 2.844 ided20 5.786 0.797 2.697 dbb0 4.048 0.947 2.847 ided19 5.751 0.831 2.731 evad15 5.971 0.611 2.511 ided18 4.236 0.759 2.659 evad14 5.886 0.696 2.596 ided17 4.229 0.766 2.666 evad13 5.659 0.923 2.823 ided16 4.275 0.720 2.620 evad12 5.842 0.740 2.640 ided15 5.815 0.767 2.667 evad11 5.852 0.731 2.631 ided14 5.832 0.750 2.650 evad10 5.927 0.655 2.555 ided13 5.866 0.717 2.617 evad9 5.914 0.668 2.568 ided12 5.829 0.754 2.654 evad8 5.923 0.660 2.560 ided11 5.834 0.748 2.648 evad7 5.981 0.606 2.506 ided10 5.861 0.721 2.621 evad6 5.992 0.595 2.495 ided9 5.817 0.765 2.665 evad5 5.917 0.666 2.566 ided8 5.853 0.729 2.629 evad4 5.965 0.618 2.518 ided7 5.843 0.739 2.639 evad3 5.949 0.639 2.539 ided6 5.841 0.741 2.641 evad2 5.730 0.852 2.752 ided5 5.898 0.684 2.584 evad1 5.942 0.641 2.541 ided4 5.892 0.690 2.590 evad0 5.799 0.783 2.683 ided3 5.856 0.726 2.626 evlkrt 6.013 0.569 2.469 ided2 5.856 0.727 2.627 chapter 7 nb85e 127 design manual a13195ej5v0dm 7. 2 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in test program execution. failure to do this will result in the propagation of undefined values. chapter 7 nb85e 128 design manual a13195ej5v0dm 7. 3 pin functions (1/4) pin name i/o function vpa13 to vpa0 output address output for peripheral macro connected to npb vpd15 to vpd0 note i/o data i/o for peripheral macro connected to npb vpwrite output write access strobe output of signals vpd15 to vpd0 vpstb output data strobe output of signals vpd15 to vpd0 vplock output bus lock output vpubenz output upper byte enable output vpretr note input retry request input from peripheral macro connected to npb npb pins vpdact input retry function control input vareq input bus access right request input vaack output bus access right acknowledge output vba27 to vba0 note i/o address i/o for peripheral macro connected to vsb vbd31 to vbd0 note i/o data i/o for peripheral macro connected to vsb vbttyp1, vbttyp0 note i/o bus transfer type i/o vbstz note i/o transfer start i/o vbbenz3 to vbbenz0 note i/o byte enable i/o vbsize1, vbsize0 note i/o transfer size i/o vbwrite note i/o read/write status i/o vblock note i/o bus lock i/o vbctyp2 to vbctyp0 note i/o bus cycle status i/o vbseq2 to vbseq0 note i/o sequential status i/o vbbstr note i/o burst read status i/o vbwait note i/o wait response i/o vblast note i/o last response i/o vbahld note i/o address hold response i/o vbdc output data bus direction control output vdcsz7 to vdcsz0 note i/o chip select i/o vsb pins vdselpz note i/o peripheral i/o area access status i/o dcresz input system reset input vbclk input internal system clock input cgrel input clock generator release input swstoprq output software stop mode request output to clock generator hwstoprq output hardware stop mode request output to clock generator dcstopz input hardware stop mode request input stprq output hardware/software stop mode request output to memc system control pins stpak input acknowledge input for input of stprq of memc note connected internally to the bus holder. chapter 7 nb85e 129 design manual a13195ej5v0dm (2/4) pin name i/o function idmastp input dma transfer terminate input dmarq3 to dmarq0 input dma transfer request input dmtco3 to dmtco0 output terminal count (dma transfer completed) output dmac pins dmactv3 to dmactv0 output dma acknowledge output dcnmi2 to dcnmi0 input non-maskable interrupt request (nmi) input intc pins int63 to int0 input maskable interrupt request input iroma19 to iroma2 output address output for rom iromz31 to iromz0 input data input for rom iromen output access enable output for rom iromwt input wait input for rom iromcs output iromia output vfb pins iromae output nec reserved pin (leave open) irama27 to irama2 output address output for ram iramz31 to iramz0 input data input for ram iraoz31 to iraoz0 output data output for ram iramen output access enable output for ram iramwr3 to iramwr0 output write enable output for ram iramrwb output read/write status output for ram vdb pins iramwt input wait input for ram ibdrrq input fetch request input from instruction cache ibea25 to ibea2 input fetch address input from instruction cache ibaack output address acknowledge output to instruction cache ibdrdy output data ready output to instruction cache ibdle3 to ibdle0 output data latch enable output to instruction cache ibedi31 to ibedi0 output data output to instruction cache iidrrq output fetch request output to instruction cache iiea25 to iiea2 output fetch address output to instruction cache iiaack input address acknowledge input from instruction cache iidlef input data latch enable input from instruction cache iiedi31 to iiedi0 input data input from instruction cache iibtft output branch target fetch status output to instruction cache iircan output code cancel status output to instruction cache bcunch output uncache status output to instruction cache instruction cache pins ibbtft input nec reserved pin (input a low level) remark vfb: v850e fetch bus vdb: v850e data bus chapter 7 nb85e 130 design manual a13195ej5v0dm (3/4) pin name i/o function iddarq output read/write access request output to data cache idaack output acknowledge output iddrrq input vsb read operation request input to bcu iddwrq input vsb write operation request input to bcu idseq4 input read/write operation type setting input idseq2 input read/write operation type setting input irrsa output vdb hold status output idretr output read retry request output idunch output uncache status output iddrdy output read data ready output idrrdy input read data ready input from data cache idhum input hit under miss-hit read input idea27 to idea0 input address input ided31 to ided0 note 1 i/o data i/o data cache pins ides output nec reserved pin note 2 dbi5 to dbi0 input debug control input dbo14 to dbo0 output debug control output rcu pins dbb15 to dbb0 note 1 i/o debug control i/o evastb input address strobe input evdstb input data strobe input evad15 to evad0 note 1 i/o address/data i/o evien output evadn input enable output (n = 15 to 0) evoen output evadn output enable output (n = 15 to 0) evlkrt note 1 i/o lock/retry i/o evirel input standby release input evclrip input ispr clear input evintak input interrupt acknowledge input evintrq output interrupt request output peripheral eva chip mode pins evintlv6 to evintlv0 output interrupt vector output ifirome input rom mapping enable input ifirob2 input location setting input of rom area ifira64 input ram area size selection input ifira32 input ram area size selection input ifira16 input ram area size selection input operation mode setting pins ifimaen input misalign access setting input notes 1. connected internally to the bus holder. 2. when using the data cache, always connect this pin to the ides pin of the data cache. leave open when unused. chapter 7 nb85e 131 design manual a13195ej5v0dm (4/4) pin name i/o function ifid256 input data area setting input ifinsz1, ifinsz0 input vsb data bus size selection input ifiwrth input data cache write-back/write-through mode selection input ifiunch1 input data cache setting input ifiunch0 input instruction cache setting input pheva input peripheral eva chip mode setting input ifirobe input ifiropr input ifirase input ifirabe input ifimode3 input ifimode2 input ifiuswe input operation mode setting pins fcomb input nec reserved pin (input a low level) tbi39 to tbi0 input input test bus tbo34 to tbo0 output output test bus test input test bus control input bunri input normal/test mode selection input phtdo1, phtdo0 note input peripheral macro test input tesen output peripheral macro test enable output vptclk output clock output for peripheral macro test phtdin1, phtdin0 output peripheral macro test output vpresz output peripheral macro reset output phtest output peripheral test mode status output tmode1 output test mode selection output tmode0 output test mode pins tbredz output nec reserved pin (leave open) note connected internally to the bus holder. chapter 7 nb85e 132 design manual a13195ej5v0dm 7. 4 electrical specifications (preliminary) the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 7. 4. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 7. 4. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 15.0 ns 7. 4. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode 0.5 0.6 ma/mhz i dd2 in halt mode (when dmac is not operating) 0.17 0.2 ma/mhz supply current i dd3 in stop mode 0 1.0 a remark the typ. value is a reference value for when t a = 25c, v dd = 3.3 v. chapter 7 nb85e 133 design manual a13195ej5v0dm 7. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) (1) clock timing parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns vbclk input high-level width <2> t kkh 7.5 ns vbclk input low-level width <3> t kkl 7.5 ns cpu operating frequency ? 066mhz (2) reset timing parameter symbol conditions min. max. unit dcresz setup time (to vbclk )<4>t skr 2.0 ns dcresz hold time (from vbclk )<5>t hkr 1.9 ns delay time from dcresz to vpresz ? t drpr 12.5 ns vbclk (input) <1> <2> <3> vbclk (input) <5> <4> <5> <4> dcresz (input) chapter 7 nb85e 134 design manual a13195ej5v0dm (3) vsb arbitration timing parameter symbol conditions min. max. unit vareq setup time (to vbclk )<6>t skq 0ns vareq hold time (from vbclk )<7>t hkq 3.4 ns delay time from vbclk to vaack <8> t dkk 1.3 4.7 ns vbclk (input) vareq (input) <7> <6> <8> vaack (output) vblock (output) vblock (external) bus master: nb85e hi-z hi-z bus master: external bus 135 design manual a13195ej5v0dm [memo] chapter 7 nb85e 136 design manual a13195ej5v0dm (4) vsb master read timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vbttyp <9> t dkt 1.3 4.1 ns vbttyp hold time (from vbclk ) <10> t hkt 2.8 ns delay time from vbclk to vba <11> t dka 1.3 6.3 ns delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp <12> t dks1 1.3 6.1 ns delay time from vbclk to vbbenz <13> t dks2 1.3 6.7 ns delay time from vbclk to vbseq, vblock <14> t dks3 1.3 6.6 ns delay time from vbclk to vdcsz, vdselpz <15> t dkc 1.3 5.6 ns delay time from vbclk to vbbstr <61> t dkbsr 1.3 5.5 ns vbd data setup time (to vbclk ) <16> t skd 0ns vbd data hold time (from vbclk ) <17> t hkd 2.8 ns vbwait, vbahld, vblast setup time (to vbclk ) <18> t skw 0ns vbwait, vbahld, vblast hold time (from vbclk ) <19> t hkw 2.9 ns delay time from vbclk to vbdc <20> t dks4 1.3 4.7 ns chapter 7 nb85e 137 design manual a13195ej5v0dm (4) vsb master read timing (2/2) remarks 1. the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85e is driving. 2. rdy: when the vbwait, vbahld, and vblast signals are all low level wait: when the vbwait signal is high level, and the vbahld and vblast signals are low level vbclk (input) vbstz (output) vba27 to vba0 (output) <9> <10> <11> address3 vbsize1, vbsize0 <12> size1 size2 size3 size4 vbwrite (output) <12> vbbenz3 to vbbenz0 <13> byte en1 byte en3 byte en4 vbseq2 to vbseq0 <14> <14> vblock (output) vbctyp2 to vbctyp0 <12> ctyp1 ctyp2 ctyp3 ctyp4 vdcsz7 to vdcsz0 (output) vdselpz (output) <15> vbwait (input) vbahld (input) vblast (input) <20> vbttyp1, vbttyp0 seq seq seq seq seq <12> rdy wait rdy rdy rdy rdy d1 d2 d3 d4 vbd31 to vbd0 (input) <18> <16> <17> <19> vbdc (output) n_seq address1 address2 byte en2 address4 <61> vbbstr (output) (output) (output) (output) (output) (output) chapter 7 nb85e 138 design manual a13195ej5v0dm (5) vsb master write timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vbttyp <9> t dkt 1.3 4.1 ns vbttyp hold time (from vbclk ) <10> t hkt 2.8 ns delay time from vbclk to vba <11> t dka 1.3 6.3 ns delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp <12> t dks1 1.3 6.1 ns delay time from vbclk to vbbenz <13> t dks2 1.3 6.7 ns delay time from vbclk to vbseq, vblock <14> t dks3 1.3 6.6 ns delay time from vbclk to vdcsz, vdselpz <15> t dkc 1.3 5.6 ns vbwait, vbahld, vblast setup time (to vbclk ) <18> t skw 0ns vbwait, vbahld, vblast hold time (from vbclk ) <19> t hkw 2.9 ns delay time from vbclk to vbdc <20> t dks4 1.3 4.7 ns delay time from vbclk to vbd data <21> t dkd0 05.5 ns delay time from vbclk to vbd data <22> t dkd1 1.2 5.8 ns chapter 7 nb85e 139 design manual a13195ej5v0dm (5) vsb master write timing (2/2) remarks 1. the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85e is driving. 2. rdy: when the vbwait, vbahld, and vblast signals are all low level wait: when the vbwait signal is high level, and the vbahld and vblast signals are low level vbclk (input) vbstz (output) vba27 to vba0 (output) <9> <10> <11> address3 address4 vbsize1, vbsize0 (output) (output) (output) (output) <12> size1 size2 size3 size4 vbwrite (output) <12> vbbenz3 to vbbenz0 <13> byte en1 byte en3 byte en4 vbseq2 to vbseq0 <14> <14> vblock (output) vbctyp2 to vbctyp0 <12> ctyp1 ctyp2 ctyp3 ctyp4 vdcsz7 to vdcsz0 (output) vdselpz (output) <15> vbwait (input) vbahld (input) vblast (input) <20> vbttyp1, vbttyp0 (output) seq seq seq seq seq <12> rdy wait rdy rdy rdy rdy data1 vbd31 to vbd0 (output) <18> <21> <19> vbdc (output) n_seq address1 address2 byte en2 <22> data2 data3 data4 chapter 7 nb85e 140 design manual a13195ej5v0dm (6) npb read timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vpstb <23> t dkp 2.5 7.8 ns vpstb output high-level width <24> t ssh 60 ns vpstb output low-level width <25> t ssl 20 ns vpa address, vpwrite, vplock, vpubenz setup time (to vpstb ) <26> t ssa 20 ns vpa address, vpwrite, vplock, vpubenz hold time (from vpstb ) <27> t hsa 20 ns vpd read data setup time (to vpstb ) <28> t ssd 20 ns vpd read data hold time (from vpstb ) <29> t hsd 0ns vpretr setup time (to vpstb ) <30> t ssr 20 ns vpretr hold time (from vpstb ) <31> t hsr 0ns vpdact setup time (to vpstb ) <32> t ssc 20 ns vpdact hold time (from vpstb ) <33> t hsc 20 ns chapter 7 nb85e 141 design manual a13195ej5v0dm (6) npb read timing (2/2) remark the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85e is driving. <26> vbclk (input) vpstb (output) <24> <25> <26> <27> data <29> <28> <26> <26> <27> <31> <30> <32> <33> address vpa13 to vpa0 (output) vpwrite (output) vpd15 to vpd0 (input) vplock (output) vpubenz (output) vpretr (input) vpdact (input) <23> <27> <27> chapter 7 nb85e 142 design manual a13195ej5v0dm (7) npb write timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vpstb <23> t dkp 2.5 7.8 ns vpstb output high-level width <24> t ssh 60 ns vpstb output low-level width <25> t ssl 20 ns vpa address, vpwrite, vplock, vpubenz setup time (to vpstb ) <26> t ssa 20 ns vpa address, vpwrite, vplock, vpubenz hold time (from vpstb ) <27> t hsa 20 ns vpd write data setup time (to vpstb ) <28> t ssd 20 ns vpd write data hold time (from vpstb ) <29> t hsd 20 ns vpretr setup time (to vpstb ) <30> t ssr 20 ns vpretr hold time (from vpstb ) <31> t hsr 0ns vpdact setup time (to vpstb ) <32> t ssc 20 ns vpdact hold time (from vpstb ) <33> t hsc 20 ns chapter 7 nb85e 143 design manual a13195ej5v0dm (7) npb write timing (2/2) remark the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85e is driving. vbclk (input) vpstb (output) <24> <25> <26> <27> <26> <26> <26> <27> <32> <33> address vpa13 to vpa0 (output) vpwrite (output) vpd15 to vpd0 (output) vplock (output) vpubenz (output) vpretr (input) vpdact (input) <28> <29> data <31> <30> <23> <27> <27> chapter 7 nb85e 144 design manual a13195ej5v0dm (8) vfb access timing parameter symbol conditions min. max. unit delay time from vbclk to iromen <34> t dkroe 1.3 8.9 ns delay time from vbclk to iroma <35> t dkroa 1.3 11.8 ns iromz setup time (to vbclk ) <36> t skroz 3.4 ns iromz hold time (from vbclk ) <37> t hkroz 3.2 ns note hold data during the iromen signal is low level. vbclk (input) iromen (output) address1 iroma19 to iroma2 (output) iromz31 to iromz0 (input) note data1 <36> data2 data3 <37> <34> <35> hold address2 address3 chapter 7 nb85e 145 design manual a13195ej5v0dm (9) vdb read timing parameter symbol conditions min. max. unit delay time from vbclk to iramrwb <38> t dkrar 1.3 8.4 ns delay time from vbclk to iramen <39> t dkrae 1.3 8.9 ns delay time from vbclk to irama <40> t dkraa 1.3 8.3 ns iramz setup time (to vbclk ) <41> t skraz 2.6 ns iramz hold time (from vbclk ) <42> t hkraz 3.7 ns note do not make signals iramz31 to iramz0 high impedance. vbclk (input) iramrwb (output) address1 irama27 to irama2 (output) iramz31 to iramz0 (input) note address2 address3 data1 <41> iramen (output) data2 data3 <42> <39> <38> <40> chapter 7 nb85e 146 design manual a13195ej5v0dm (10) vdb write timing parameter symbol conditions min. max. unit delay time from vbclk to iramwr <43> t dkraw 1.3 8.8 ns delay time from vbclk to iraoz <44> t dkraz 1.3 9.1 ns note signals iraoz31 to iraoz0 are always output and do not become high impedance. write operations are controlled by the iramen signal and signals iramwr3 to iramwr0. data cannot be written when the iramen signal is low level. vbclk (input) iramrwb (output) address1 irama27 to irama2 (output) address2 address3 iramen (output) iraoz31 to iraoz0 (output) note iramwr3 to iramwr0 (output) <43> we1 we2 we3 <44> data1 data2 data3 chapter 7 nb85e 147 design manual a13195ej5v0dm (11) dma transfer request, transfer completion timing parameter symbol conditions min. max. unit dmarq setup time (to vbclk ) <45> t skdq 0ns dmarq hold time (from vbclk ) <46> t hkdq 0.8 ns delay time from vbclk to dmactv, dmtco <47> t dkdc 1.3 6.5 ns note in order to avoid the generation of the next cycle, make the dmarqn signal low level in this cycle. remark n = 3 to 0 (12) dma transfer abort timing parameter symbol conditions min. max. unit idmastp setup time (to vbclk ) <48> t skds 3.5 ns idmastp hold time (from vbclk ) <49> t hkds 1.7 ns note input using a 1-clock pulse. vbclk (input) dmactvn (output) dmarqn (input) <45> <46> note <47> <47> dmtcon (output) <45> vbclk (input) idmastp (input) note <49> <48> chapter 7 nb85e 148 design manual a13195ej5v0dm (13) software stop mode timing parameter symbol conditions min. max. unit delay time from vbclk to stprq <50> t dksq 1.3 4.6 ns stpak setup time (to vbclk ) <51> t sksa 0ns stpak hold time (from stprq ) <52> t hqsa 7.0 ns delay time from vbclk to swstoprq <53> t dkss 1.3 4.7 ns delay time from int, dcnmi to swstoprq <54> t drsr 0 15.0 ns cgrel setup time (to vbclk ) <55> t sksg 0ns cgrel hold time (from vbclk ) <56> t hksg 2.5 ns notes 1. software stop mode is released upon detection of the rising edge of these signals. 2. input an active level (high level) of 1 clock or more. vbclk (input) stprq (output) <50> <50> <51> <52> <53> <54> <56> stpak (input) swstoprq (output) int63 to int0 (input) note 1 dcnmi2 to dcnmi0 (input) note 1 cgrel (input) note 2 <55> chapter 7 nb85e 149 design manual a13195ej5v0dm (14) hardware stop mode timing parameter symbol conditions min. max. unit delay time from vbclk to stprq <50> t dksq 1.3 4.6 ns stpak setup time (to vbclk ) <51> t sksa 0ns stpak hold time (from stprq ) <52> t hqsa 7.0 ns delay time from vbclk to hwstoprq <53> t dkss 1.3 4.7 ns delay time from dcstopz to hwstoprq <54> t drsr 0 15.0 ns cgrel setup time (to vbclk ) <55> t sksg 0ns cgrel hold time (from vbclk ) <56> t hksg 2.5 ns dcstopz setup time (to vbclk ) <57> t skst 0ns notes 1. hardware stop mode is released upon detection of the rising edge of this signal. 2. input an active level (high level) of 1 clock or more. vbclk (input) stprq (output) <50> <50> <51> <52> <53> <54> <56> stpak (input) hwstoprq (output) dcstopz (input) note 1 cgrel (input) note 2 <57> <55> chapter 7 nb85e 150 design manual a13195ej5v0dm (15) interrupt timing parameter symbol conditions min. max. unit int, dcnmi high-level width <58> t wih 5.0 ns int, dcnmi low-level width <59> t wil 5.0 ns int, dcnmi interval time <60> t cyi 3 t cyk ns note an interrupt is generated upon detection of the rising edge of these signals. int63 to int0 (input) note dcnmi2 to dcnmi0 (input) note <58> <59> <60> 151 design manual a13195ej5v0dm chapter 8 nb85e901 (under development) the nb85e901 is a run control unit (rcu) used by connecting to the nb85e. 8. 1 outline the nb85e901 (rcu) is a run control unit that realizes the execution of jtag communication and debug processing. connection of the nb85e901 with an n-wire type in-circuit emulator (n-wire type ie) makes it possible to perform on-chip debugging on the nb85e. 8. 1. 1 symbol diagram number of grids 36.2k grids 46.4k grids (including wiring area) number of separation simulation patterns 41.8k out in out in in in/out in dbint resetz stopz nmi (2:0) vareq dms ddi ddo drstz dck in in in in out in in in vbclk dbi (5:0) dbo (14:0) dbb (15:0) tmode1 vbwait dcresz dcstopz bunri in test in in in out romtype dcop (13:0) out in dcnmi (2:0) dcvareq vbtclk dcwaitz stpak out out in out in waitz in chapter 8 nb85e901 152 design manual a13195ej5v0dm 8. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) dck 0.027 1.927 dbo10 0.020 1.920 drstz 0.017 1.917 dbo9 0.054 1.954 dms 0.088 1.988 dbo8 0.024 1.924 ddi 0.054 1.954 dbo7 0.062 1.962 dbint 0.019 1.919 dbo6 0.077 1.977 resetz 0.069 1.969 dbo5 0.048 1.948 stopz 0.066 1.966 dbo4 0.057 1.957 nmi2 0.036 1.936 dbo3 0.065 1.965 nmi1 0.063 1.963 dbo2 0.090 1.990 nmi0 0.048 1.948 dbo1 0.009 1.909 vareq 0.021 1.921 dbo0 0.067 1.967 waitz 0.024 1.924 tmode1 0.029 1.929 romtype 0.132 2.032 vbwait 0.050 1.950 vbclk 0.035 1.935 vbtclk 0.040 1.940 dbo14 0.057 1.957 stpak 0.014 1.914 dbo13 0.062 1.962 bunri 0.096 1.996 dbo12 0.079 1.979 test 0.034 1.934 dbo11 0.065 1.965 (2) output pins pin name c max (pf) pin name c max (pf) pin name c max (pf) ddo 6.518 dcop4 6.482 dbi0 12.901 dcop13 6.399 dcop3 6.474 dcresz 6.462 dcop12 6.306 dcop2 6.399 dcstopz 4.884 dcop11 6.404 dcop1 6.560 dcnmi2 13.191 dcop10 6.358 dcop0 6.553 dcnmi1 13.319 dcop9 12.922 dbi5 12.958 dcnmi0 13.308 dcop8 12.855 dbi4 4.555 dcvareq 13.201 dcop7 12.917 dbi3 6.435 dcwaitz 13.306 dcop6 12.818 dbi2 13.311 dcop5 12.850 dbi1 6.462 chapter 8 nb85e901 153 design manual a13195ej5v0dm (3) i/o pins pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) dbb15 6.487 0.095 1.995 dbb7 6.462 0.120 2.020 dbb14 6.420 0.163 2.063 dbb6 6.451 0.132 2.032 dbb13 6.492 0.091 1.991 dbb5 6.389 0.194 2.094 dbb12 6.432 0.150 2.050 dbb4 6.373 0.210 2.110 dbb11 6.517 0.066 1.966 dbb3 6.443 0.139 2.039 dbb10 6.524 0.059 1.959 dbb2 6.412 0.170 2.070 dbb9 6.487 0.096 1.996 dbb1 6.466 0.116 2.016 dbb8 6.496 0.087 1.987 dbb0 6.384 0.199 2.099 chapter 8 nb85e901 154 design manual a13195ej5v0dm 8. 2 pin functions pin name i/o function dck input clock input for rcu drstz input reset input for rcu dms input debug mode selection input ddi input debug data input ddo output debug data output n-wire type ie connection pins dbint input external debug interrupt input resetz input system reset input stopz input hardware stop mode request input nmi2 to nmi0 input non-maskable interrupt input vareq input bus access right request input waitz input wait request input romtype input nec reserved pin (input a low level) system control pins dcop13 to dcop0 output nec reserved pin (leave open) vbclk input system clock input dbi5 to dbi0 output debug control output dbo14 to dbo0 input debug control input dbb15 to dbb0 i/o debug control i/o tmode1 input test mode selection input vbwait input wait response input dcresz output reset output dcstopz output hardware stop mode request output dcnmi2 to dcnmi0 output non-maskable interrupt output dcvareq output bus access right request output nb85e connection pins vbtclk input clock input for testing dcwaitz output wait request output peripheral connection pins stpak input stop mode request acknowledge input bunri input normal/test mode selection input test mode pins test input test bus control input chapter 8 nb85e901 155 design manual a13195ej5v0dm 8. 3 electrical specifications (preliminary) the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 8. 3. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 8. 3. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 15.0 ns 8. 3. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1 when operating 0.33 0.43 ma/mhz supply current i dd2 when not operating 0 1.0 a remark the typ. value is a reference value for when t a = 25c, v dd = 3.3 v. 8. 3. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. max. unit delay time from resetz to dcresz t ddres 2.0 ns delay time from stopz to dcstopz t ddstp 2.0 ns delay time from nmi to dcnmi t ddnmi 2.0 ns delay time from waitz to dcwaitz t ddwt 2.0 ns delay time from vareq to dcvareq t ddvrq 2.0 ns 156 design manual a13195ej5v0dm chapter 9 nb85et (under development) the nb85et is a cpu core incorporating debug controller that realizes on-chip debugging using a single nb85et, and includes on chip the ?v850e1? cpu, nec?s 32-bit risc microprocessor, as well as various peripheral i/o functions such as dma and interrupt controllers. 9. 1 outline ? processing performance: 62 mips (@ 50 mhz operation) ? memory space program area: 64 mb linear data area: 4 gb linear memory bank division function: 2, 4, and 8 mb/bank ? minimum instruction execution time: 20 ns (@ 50 mhz operation) ? external bus interface vsb (v850e system bus) npb (nec peripheral i/o bus) ? interrupt/exception control function non-maskable interrupts: 3 sources maskable interrupts: 64 sources exceptions: 1 source 8 priority levels specifiable (maskable interrupts) ? dma control function 4-channel structure transfer unit: 8, 16, and 32 bits maximum number of transfers: 65536 (2 16 ) transfer type: flyby (1-cycle) transfer, 2-cycle transfer transfer mode: single transfer, single step transfer, line transfer, block transfer terminal count output signals (dmtco3 to dmtco0) ? power save function halt, hardware/software stop modes ? debug control function cpu break, trace, event detection chapter 9 nb85et 157 design manual a13195ej5v0dm 9. 1. 1 symbol diagram number of grids 574.6k grids 857.4k grids (including wiring area) number of separation simulation patterns 498.5k chapter 9 nb85et 158 design manual a13195ej5v0dm evirel in vaack vareq idmastp in dmarq in dmtco out dmactv out ibdrrq ibea ibaack ibdrdy ibdle ibedi ibbtft iidrrq iiea iiaack iidlef iiedi iibtft iircan bcunch vptclk out phtest out tesen out tbo out cgrel swstoprq hwstoprq stopz stprq tbredz out out vpa in/out vpd out vpwrite out vpstb out out in in vplock vpubenz vpretr vpdact vdselpz vdcsz vbseq vbctyp vbsize vbbenz vbttyp vbd in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out out in/out in/out vba vbstz vbwrite vblock vbbstr vbwait vblast vbahld vbdc resetz vbclk test in bunri in out phtdin in phtdo iroma out iromz in iromen out iromcs out iromia out iromae out iromwt in irama out iramz in iramen out iramwr out iramrwb out iraoz out iramwt in out tmode tbi in int nmi in in vpresz out iddarq iddrrq iddwrq idaack idseq2 idseq4 irrsa idretr ides iddrdy idrrdy idhum idea ided idunch out in in out in in out out out out out in in in in/out evastb evdstb evad evlkrt evc lrip evintak evintrq evintlv evien evoen in in in/out out out in/out in in out out ifinsz ifirome ifirob2 ifirobe ifiropr ifimode2 ifira16 ifira32 ifira64 ifirase ifirabe ifiuswe ifimaen ifid256 ifiunch fcomb pheva ifiwrth ifimode3 in in in in in in in in in in in in in in in in in in in out out out out in in in in in in out out out out out out in in in out out out in stpak ddo out trcclk out trcdata out trcend out evttrg out ddoout out ddoenb out dbresz out resmk out mskstp out dcwait out dcresz out exhlt out msknmi out mskhrq out dbrdy out tapsm out idbr out dck in dms in ddi in dbint in romtype in mwait in trg out drstz in clkb1 eintak eclrip ifieva eintrq eintlv (6:0) in out out in in in in out (1:0) (1:0) (27:0) (31:0) (19:2) (31:0) (27:2) (31:0) (31:0) (3:0) (2:0) (63:0) (3:0) (3:0) (3:0) (13:0) (15:0) (39:0) (34:0) (1:0) (1:0) (1:0) (2:0) (3:0) (1:0) (2:0) (3:0) (6:0) (15:0) (7:0) (2:0) (2:0) (3:0) (1:0) (27:0) (31:0) (1:0) (31:0) (25:2) (31:0) (3:0) (25:2) chapter 9 nb85et 159 design manual a13195ej5v0dm 9. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins (1/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) vpretr 0.663 2.563 int45 0.032 1.932 vpdact 0.205 2.105 int44 0.052 1.952 vareq 0.248 2.148 int43 0.032 1.932 resetz 0.196 2.096 int42 0.023 1.923 vbclk 0.070 1.970 int41 0.051 1.951 cgrel 0.047 1.947 int40 0.084 1.984 stopz 0.447 2.347 int39 0.228 2.128 stpak 0.263 2.163 int38 0.070 1.970 idmastp 0.137 2.037 int37 0.075 1.975 dmarq3 0.020 1.920 int36 0.088 1.988 dmarq2 0.211 2.111 int35 0.071 1.971 dmarq1 0.169 2.069 int34 0.033 1.933 dmarq0 0.259 2.159 int33 0.053 1.953 nmi2 0.390 2.290 int32 0.031 1.931 nmi1 0.340 2.240 int31 0.039 1.939 nmi0 0.363 2.263 int30 0.050 1.950 int63 0.022 1.922 int29 0.024 1.924 int62 0.031 1.931 int28 0.042 1.942 int61 0.013 1.913 int27 0.013 1.913 int60 0.023 1.923 int26 0.044 1.944 int59 0.034 1.934 int25 0.012 1.912 int58 0.032 1.932 int24 0.017 1.917 int57 0.046 1.946 int23 0.053 1.953 int56 0.024 1.924 int22 0.058 1.958 int55 0.016 1.916 int21 0.019 1.919 int54 0.057 1.957 int20 0.019 1.919 int53 0.016 1.916 int19 0.034 1.934 int52 0.033 1.933 int18 0.019 1.919 int51 0.054 1.954 int17 0.045 1.945 int50 0.043 1.943 int16 0.023 1.923 int49 0.015 1.915 int15 0.027 1.927 int48 0.025 1.925 int14 0.016 1.916 int47 0.020 1.920 int13 0.044 1.944 int46 0.057 1.957 int12 0.034 1.934 chapter 9 nb85et 160 design manual a13195ej5v0dm (1) input pins (2/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) int11 0.034 1.934 iromz4 0.651 2.551 int10 0.023 1.923 iromz3 0.612 2.512 int9 0.037 1.937 iromz2 0.707 2.607 int8 0.028 1.928 iromz1 0.599 2.499 int7 0.024 1.924 iromz0 0.632 2.532 int6 0.026 1.926 iromwt 0.117 2.017 int5 0.028 1.928 iramz31 0.057 1.957 int4 0.030 1.930 iramz30 0.037 1.937 int3 0.025 1.925 iramz29 0.513 2.413 int2 0.035 1.935 iramz28 0.483 2.383 int1 0.026 1.926 iramz27 0.198 2.098 int0 0.030 1.930 iramz26 0.036 1.936 iromz31 0.318 2.218 iramz25 0.051 1.951 iromz30 0.405 2.305 iramz24 0.045 1.945 iromz29 0.313 2.213 iramz23 0.036 1.936 iromz28 0.358 2.258 iramz22 0.037 1.937 iromz27 0.534 2.434 iramz21 0.152 2.052 iromz26 0.411 2.311 iramz20 0.473 2.373 iromz25 0.352 2.252 iramz19 0.380 2.280 iromz24 0.427 2.327 iramz18 0.209 2.109 iromz23 0.373 2.273 iramz17 0.233 2.133 iromz22 0.527 2.427 iramz16 0.078 1.978 iromz21 0.544 2.444 iramz15 0.075 1.975 iromz20 0.335 2.235 iramz14 0.052 1.952 iromz19 0.406 2.306 iramz13 0.239 2.139 iromz18 0.603 2.503 iramz12 0.197 2.097 iromz17 0.400 2.300 iramz11 0.234 2.134 iromz16 0.399 2.299 iramz10 0.184 2.084 iromz15 0.388 2.288 iramz9 0.407 2.307 iromz14 0.569 2.469 iramz8 0.222 2.122 iromz13 0.559 2.459 iramz7 0.322 2.222 iromz12 0.597 2.497 iramz6 0.063 1.963 iromz11 0.612 2.512 iramz5 0.278 2.178 iromz10 0.643 2.543 iramz4 0.265 2.165 iromz9 0.375 2.275 iramz3 0.241 2.141 iromz8 0.434 2.334 iramz2 0.169 2.069 iromz7 0.602 2.502 iramz1 0.050 1.950 iromz6 0.399 2.299 iramz0 0.292 2.192 iromz5 0.537 2.437 iramwt 0.393 2.293 chapter 9 nb85et 161 design manual a13195ej5v0dm (1) input pins (3/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) ibdrrq 0.110 2.010 iiedi19 0.043 1.943 ibea25 0.168 2.068 iiedi18 0.084 1.984 ibea24 0.110 2.010 iiedi17 0.075 1.975 ibea23 0.014 1.914 iiedi16 0.042 1.942 ibea22 0.025 1.925 iiedi15 0.067 1.967 ibea21 0.074 1.974 iiedi14 0.070 1.970 ibea20 0.017 1.917 iiedi13 0.049 1.949 ibea19 0.050 1.950 iiedi12 0.047 1.947 ibea18 0.057 1.957 iiedi11 0.054 1.954 ibea17 0.014 1.914 iiedi10 0.022 1.922 ibea16 0.043 1.943 iiedi9 0.056 1.956 ibea15 0.016 1.916 iiedi8 0.038 1.938 ibea14 0.024 1.924 iiedi7 0.049 1.949 ibea13 0.139 2.039 iiedi6 0.038 1.938 ibea12 0.032 1.932 iiedi5 0.029 1.929 ibea11 0.109 2.009 iiedi4 0.038 1.938 ibea10 0.150 2.050 iiedi3 0.029 1.929 ibea9 0.082 1.982 iiedi2 0.022 1.922 ibea8 0.125 2.025 iiedi1 0.030 1.930 ibea7 0.133 2.033 iiedi0 0.020 1.920 ibea6 0.128 2.028 ibbtft 0.175 2.075 ibea5 0.117 2.017 iddrrq 0.549 2.449 ibea4 0.089 1.989 iddwrq 0.522 2.422 ibea3 0.168 2.068 idseq4 0.373 2.273 ibea2 0.180 2.080 idseq2 0.568 2.468 iiaack 0.069 1.969 idrrdy 0.155 2.055 iidlef 0.090 1.990 idhum 0.361 2.261 iiedi31 0.159 2.059 idea27 0.249 2.149 iiedi30 0.143 2.043 idea26 0.264 2.164 iiedi29 0.124 2.024 idea25 0.293 2.193 iiedi28 0.110 2.010 idea24 0.375 2.275 iiedi27 0.115 2.015 idea23 0.255 2.155 iiedi26 0.094 1.994 idea22 0.260 2.160 iiedi25 0.178 2.078 idea21 0.251 2.151 iiedi24 0.124 2.024 idea20 0.356 2.256 iiedi23 0.105 2.005 idea19 0.259 2.159 iiedi22 0.081 1.981 idea18 0.333 2.233 iiedi21 0.083 1.983 idea17 0.248 2.148 iiedi20 0.066 1.966 idea16 0.273 2.173 chapter 9 nb85et 162 design manual a13195ej5v0dm (1) input pins (4/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) idea15 0.328 2.228 ifira32 0.944 2.844 idea14 0.291 2.191 ifira16 0.831 2.731 idea13 0.303 2.203 ifimaen 0.430 2.330 idea12 0.325 2.225 ifid256 0.450 2.350 idea11 0.248 2.148 ifinsz1 0.476 2.376 idea10 0.361 2.261 ifinsz0 0.491 2.391 idea9 0.328 2.228 ifiwrth 0.549 2.449 idea8 0.256 2.156 ifiunch1 0.657 2.557 idea7 0.249 2.149 ifiunch0 0.506 2.406 idea6 0.344 2.244 pheva 1.405 3.305 idea5 0.235 2.135 ifieva 0.311 2.211 idea4 0.244 2.144 ifimode2 0.586 2.486 idea3 0.235 2.135 ifirobe 0.413 2.313 idea2 0.274 2.174 ifiropr 0.523 2.423 idea1 0.259 2.159 ifirase 1.053 2.953 idea0 0.234 2.134 ifirabe 0.610 2.510 eintlv6 0.034 1.934 ifimode3 0.642 2.542 eintlv5 0.062 1.962 ifiuswe 0.377 2.277 eintlv4 0.040 1.940 fcomb 0.131 2.031 eintlv3 0.013 1.913 tbi39 0.013 1.913 eintlv2 0.066 1.966 tbi38 0.013 1.913 eintlv1 0.046 1.946 tbi37 0.060 1.960 eintlv0 0.055 1.955 tbi36 0.034 1.934 eintrq 0.048 1.948 tbi35 0.023 1.923 dck 0.408 2.308 tbi34 0.007 1.907 dms 0.196 2.096 tbi33 0.031 1.931 ddi 0.016 1.916 tbi32 0.014 1.914 drstz 0.014 1.914 tbi31 0.017 1.917 mwait 0.065 1.965 tbi30 0.017 1.917 dbint 0.074 1.974 tbi29 0.021 1.921 romtype 0.080 1.980 tbi28 0.011 1.911 evastb 0.410 2.310 tbi27 0.028 1.928 evdstb 0.181 2.081 tbi26 0.018 1.918 evirel 0.135 2.035 tbi25 0.010 1.910 evclrip 0.225 2.125 tbi24 0.023 1.923 evintak 0.133 2.033 tbi23 0.021 1.921 ifirome 0.462 2.362 tbi22 0.034 1.934 ifirob2 0.550 2.450 tbi21 0.158 2.058 ifira64 1.016 2.916 tbi20 0.168 2.068 chapter 9 nb85et 163 design manual a13195ej5v0dm (1) input pins (5/5) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) tbi19 0.103 2.003 tbi7 0.022 1.922 tbi18 0.186 2.086 tbi6 0.047 1.947 tbi17 0.190 2.090 tbi5 0.032 1.932 tbi16 0.171 2.071 tbi4 0.013 1.913 tbi15 0.008 1.908 tbi3 0.016 1.916 tbi14 0.032 1.932 tbi2 0.007 1.907 tbi13 0.041 1.941 tbi1 0.043 1.943 tbi12 0.031 1.931 tbi0 0.025 1.925 tbi11 0.042 1.942 test 0.305 2.205 tbi10 0.041 1.941 bunri 0.459 2.359 tbi9 0.025 1.925 phtdo1 0.545 2.445 tbi8 0.031 1.931 phtdo0 0.540 2.440 (2) output pins (1/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vpa13 12.854 ?? stprq 12.443 ?? vpa12 12.877 ?? dmtco3 12.973 ?? vpa11 12.799 ?? dmtco2 12.905 ?? vpa10 13.300 ?? dmtco1 13.145 ?? vpa9 12.852 ?? dmtco0 13.157 ?? vpa8 12.801 ?? dmactv3 13.185 ?? vpa7 13.284 ?? dmactv2 13.275 ?? vpa6 13.272 ?? dmactv1 13.229 ?? vpa5 13.242 ?? dmactv0 13.338 ?? vpa4 13.102 ?? iroma19 13.056 ?? vpa3 13.149 ?? iroma18 13.071 ?? vpa2 13.192 ?? iroma17 13.069 ?? vpa1 12.839 ?? iroma16 13.069 ?? vpa0 13.188 ?? iroma15 13.068 ?? vpwrite 13.151 ?? iroma14 13.334 ?? vpstb 12.758 ?? iroma13 13.333 ?? vplock 13.025 ?? iroma12 13.332 ?? vpubenz 13.191 ?? iroma11 13.055 ?? vaack 12.977 ?? iroma10 13.329 ?? vbdc 13.018 ?? iroma9 13.064 ?? clkb1 13.071 ?? iroma8 13.328 ?? swstoprq 12.778 ?? iroma7 13.338 ?? hwstoprq 12.945 ?? iroma6 13.062 ?? chapter 9 nb85et 164 design manual a13195ej5v0dm (2) output pins (2/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) iroma5 13.071 ?? iraoz26 13.291 ?? iroma4 13.059 ?? iraoz25 13.331 ?? iroma3 13.046 ?? iraoz24 13.286 ?? iroma2 13.052 ?? iraoz23 13.326 ?? iromen 13.056 ?? iraoz22 13.334 ?? iromcs 13.055 ?? iraoz21 13.336 ?? iromia 12.985 ?? iraoz20 13.336 ?? iromae 13.006 ?? iraoz19 13.327 ?? irama27 13.071 ?? iraoz18 13.312 ?? irama26 13.291 ?? iraoz17 13.269 ?? irama25 13.006 ?? iraoz16 13.103 ?? irama24 13.322 ?? iraoz15 13.260 ?? irama23 13.325 ?? iraoz14 13.314 ?? irama22 13.332 ?? iraoz13 13.335 ?? irama21 13.009 ?? iraoz12 13.292 ?? irama20 13.325 ?? iraoz11 13.118 ?? irama19 13.323 ?? iraoz10 13.275 ?? irama18 13.297 ?? iraoz9 13.333 ?? irama17 13.283 ?? iraoz8 13.257 ?? irama16 13.303 ?? iraoz7 13.338 ?? irama15 13.269 ?? iraoz6 13.314 ?? irama14 13.324 ?? iraoz5 13.334 ?? irama13 13.317 ?? iraoz4 13.321 ?? irama12 13.323 ?? iraoz3 13.194 ?? irama11 13.320 ?? iraoz2 13.112 ?? irama10 13.272 ?? iraoz1 13.331 ?? irama9 13.284 ?? iraoz0 13.338 ?? irama8 13.311 ?? iramen 13.194 ?? irama7 13.270 ?? iramwr3 13.139 ?? irama6 13.274 ?? iramwr2 13.152 ?? irama5 13.270 ?? iramwr1 13.202 ?? irama4 13.273 ?? iramwr0 13.262 ?? irama3 13.329 ?? iramrwb 13.191 ?? irama2 13.319 ?? ibaack 13.338 ?? iraoz31 13.337 ?? ibdrdy 13.338 ?? iraoz30 13.334 ?? ibdle3 12.818 ?? iraoz29 13.338 ?? ibdle2 12.785 ?? iraoz28 13.333 ?? ibdle1 12.744 ?? iraoz27 13.333 ?? ibdle0 12.620 ?? chapter 9 nb85et 165 design manual a13195ej5v0dm (2) output pins (3/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) ibedi31 12.929 ?? iiea19 13.035 ?? ibedi30 12.948 ?? iiea18 13.061 ?? ibedi29 13.056 ?? iiea17 13.070 ?? ibedi28 12.980 ?? iiea16 13.048 ?? ibedi27 13.025 ?? iiea15 13.071 ?? ibedi26 13.017 ?? iiea14 13.070 ?? ibedi25 12.969 ?? iiea13 12.948 ?? ibedi24 13.000 ?? iiea12 13.057 ?? ibedi23 12.990 ?? iiea11 12.956 ?? ibedi22 13.039 ?? iiea10 12.981 ?? ibedi21 13.044 ?? iiea9 13.028 ?? ibedi20 13.051 ?? iiea8 13.005 ?? ibedi19 13.049 ?? iiea7 13.026 ?? ibedi18 13.041 ?? iiea6 13.067 ?? ibedi17 13.033 ?? iiea5 12.964 ?? ibedi16 13.067 ?? iiea4 12.999 ?? ibedi15 13.027 ?? iiea3 12.929 ?? ibedi14 13.024 ?? iiea2 12.948 ?? ibedi13 13.061 ?? iibtft 12.924 ?? ibedi12 13.052 ?? iircan 12.889 ?? ibedi11 13.048 ?? bcunch 13.062 ?? ibedi10 13.070 ?? iddarq 13.037 ?? ibedi9 13.038 ?? idaack 13.030 ?? ibedi8 13.059 ?? irrsa 13.287 ?? ibedi7 13.054 ?? idretr 13.039 ?? ibedi6 13.046 ?? idunch 12.574 ?? ibedi5 13.067 ?? iddrdy 13.289 ?? ibedi4 13.066 ?? ides 13.049 ?? ibedi3 13.066 ?? eintak 13.025 ?? ibedi2 13.066 ?? eclrip 13.049 ?? ibedi1 13.060 ?? ddo 13.007 ?? ibedi0 13.065 ?? trcclk 12.885 ?? iidrrq 13.019 ?? trcdata3 12.803 ?? iiea25 12.985 ?? trcdata2 12.796 ?? iiea24 12.972 ?? trcdata1 12.683 ?? iiea23 13.070 ?? trcdata0 12.852 ?? iiea22 13.067 ?? trcend 12.736 ?? iiea21 13.020 ?? idbr2 12.638 ?? iiea20 13.056 ?? idbr1 12.206 ?? chapter 9 nb85et 166 design manual a13195ej5v0dm (2) output pins (4/4) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) idbr0 12.673 ?? tbo27 6.493 0.137 2.037 evttrg 13.238 ?? tbo26 6.276 0.353 2.253 dcresz 13.071 ?? tbo25 6.396 0.233 2.133 dcwait 12.844 ?? tbo24 6.470 0.159 2.059 exhlt 12.343 ?? tbo23 6.575 0.055 1.955 ddoout 12.869 ?? tbo22 6.484 0.145 2.045 ddoenb 12.829 ?? tbo21 6.578 0.051 1.951 tapsm3 12.942 ?? tbo20 6.576 0.053 1.953 tapsm2 12.851 ?? tbo19 6.496 0.133 2.033 tapsm1 12.885 ?? tbo18 6.515 0.114 2.014 tapsm0 12.857 ?? tbo17 6.487 0.142 2.042 trg1 12.976 ?? tbo16 6.505 0.124 2.024 trg0 12.610 ?? tbo15 6.571 0.058 1.958 dbresz 13.149 ?? tbo14 6.578 0.052 1.952 resmk 13.316 ?? tbo13 6.577 0.052 1.952 mskstp 13.011 ?? tbo12 6.579 0.050 1.950 msknmi2 12.807 ?? tbo11 6.581 0.048 1.948 msknmi1 12.691 ?? tbo10 6.565 0.064 1.964 msknmi0 12.690 ?? tbo9 6.576 0.053 1.953 mskhrq 13.274 ?? tbo8 6.556 0.074 1.974 dbrdy 13.243 ?? tbo7 6.571 0.058 1.958 evien 13.192 ?? tbo6 6.561 0.068 1.968 evoen 13.328 ?? tbo5 6.561 0.068 1.968 evintrq 13.324 ?? tbo4 6.573 0.056 1.956 evintlv6 13.028 ?? tbo3 6.561 0.068 1.968 evintlv5 12.762 ?? tbo2 6.571 0.059 1.959 evintlv4 12.936 ?? tbo1 6.566 0.063 1.963 evintlv3 13.012 ?? tbo0 6.562 0.067 1.967 evintlv2 13.183 ?? tesen 13.064 ?? evintlv1 13.252 ?? vptclk 13.054 ?? evintlv0 13.006 ?? phtdin1 13.071 ?? tbo34 6.581 0.048 1.948 phtdin0 13.071 ?? tbo33 6.577 0.052 1.952 vpresz 13.304 ?? tbo32 6.572 0.057 1.957 phtest 13.054 ?? tbo31 6.569 0.060 1.960 tmode1 12.802 ?? tbo30 6.581 0.048 1.948 tmode0 12.737 ?? tbo29 6.576 0.053 1.953 tbredz 13.338 ?? tbo28 6.578 0.051 1.951 chapter 9 nb85et 167 design manual a13195ej5v0dm (3) i/o pins (1/2) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vpd15 5.926 0.703 2.603 vba4 5.515 1.161 3.061 vpd14 5.903 0.727 2.627 vba3 5.472 1.204 3.104 vpd13 5.877 0.752 2.652 vba2 5.492 1.184 3.084 vpd12 5.841 0.788 2.688 vba1 5.833 0.842 2.742 vpd11 5.871 0.758 2.658 vba0 5.772 0.903 2.803 vpd10 5.891 0.738 2.638 vbd31 5.156 1.520 3.420 vpd9 5.892 0.737 2.637 vbd30 5.261 1.414 3.314 vpd8 5.897 0.732 2.632 vbd29 5.218 1.457 3.357 vpd7 5.886 0.744 2.644 vbd28 5.245 1.431 3.331 vpd6 5.846 0.783 2.683 vbd27 4.763 1.913 3.813 vpd5 5.774 0.855 2.755 vbd26 4.889 1.786 3.686 vpd4 5.741 0.888 2.788 vbd25 5.085 1.591 3.491 vpd3 5.768 0.861 2.761 vbd24 5.168 1.508 3.408 vpd2 5.867 0.762 2.662 vbd23 5.204 1.471 3.371 vpd1 5.836 0.793 2.693 vbd22 5.135 1.541 3.441 vpd0 5.860 0.769 2.669 vbd21 4.962 1.714 3.614 vba27 5.944 0.731 2.631 vbd20 4.982 1.694 3.594 vba26 5.915 0.760 2.660 vbd19 4.801 1.875 3.775 vba25 5.986 0.690 2.590 vbd18 4.973 1.703 3.603 vba24 5.985 0.691 2.591 vbd17 5.199 1.477 3.377 vba23 5.945 0.731 2.631 vbd16 4.879 1.797 3.697 vba22 5.920 0.756 2.656 vbd15 3.517 1.607 3.507 vba21 5.932 0.744 2.644 vbd14 3.581 1.542 3.442 vba20 5.935 0.741 2.641 vbd13 4.948 1.775 3.675 vba19 5.915 0.761 2.661 vbd12 5.215 1.507 3.407 vba18 5.819 0.857 2.757 vbd11 4.863 1.860 3.760 vba17 5.906 0.770 2.670 vbd10 3.578 1.546 3.446 vba16 5.910 0.765 2.665 vbd9 3.435 1.688 3.588 vba15 5.922 0.754 2.654 vbd8 3.500 1.624 3.524 vba14 5.905 0.771 2.671 vbd7 4.892 1.831 3.731 vba13 5.656 1.020 2.920 vbd6 3.637 1.487 3.387 vba12 5.790 0.886 2.786 vbd5 3.535 1.588 3.488 vba11 5.491 1.185 3.085 vbd4 3.528 1.596 3.496 vba10 5.531 1.145 3.045 vbd3 4.727 1.996 3.896 vba9 5.630 1.046 2.946 vbd2 3.492 1.631 3.531 vba8 5.652 1.024 2.924 vbd1 3.463 1.661 3.561 vba7 5.415 1.260 3.160 vbd0 4.814 1.909 3.809 vba6 5.430 1.245 3.145 vbttyp1 5.956 0.719 2.619 vba5 5.438 1.238 3.138 vbttyp0 5.982 0.694 2.594 chapter 9 nb85et 168 design manual a13195ej5v0dm (3) i/o pins (2/2) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vbstz 5.750 0.925 2.825 ided20 5.929 0.700 2.600 vbbenz3 5.984 0.691 2.591 ided19 5.956 0.673 2.573 vbbenz2 6.001 0.674 2.574 ided18 5.987 0.642 2.542 vbbenz1 5.847 0.829 2.729 ided17 5.940 0.689 2.589 vbbenz0 6.006 0.670 2.570 ided16 5.895 0.734 2.634 vbsize1 5.884 0.792 2.692 ided15 5.884 0.745 2.645 vbsize0 5.898 0.778 2.678 ided14 5.876 0.753 2.653 vbwrite 5.725 0.950 2.850 ided13 5.998 0.631 2.531 vblock 5.820 0.856 2.756 ided12 5.937 0.692 2.592 vbctyp2 5.904 0.771 2.671 ided11 5.915 0.714 2.614 vbctyp1 5.955 0.721 2.621 ided10 5.923 0.706 2.606 vbctyp0 5.941 0.735 2.635 ided9 5.891 0.739 2.639 vbseq2 5.952 0.724 2.624 ided8 5.917 0.713 2.613 vbseq1 5.957 0.719 2.619 ided7 5.985 0.645 2.545 vbseq0 5.971 0.704 2.604 ided6 6.021 0.608 2.508 vbbstr 5.972 0.704 2.604 ided5 5.828 0.801 2.701 vbwait 4.961 1.715 3.615 ided4 5.858 0.771 2.671 vblast 5.842 0.834 2.734 ided3 5.901 0.729 2.629 vbahld 5.771 0.905 2.805 ided2 6.034 0.595 2.495 vdcsz7 6.017 0.659 2.559 ided1 6.031 0.598 2.498 vdcsz6 6.044 0.632 2.532 ided0 5.928 0.701 2.601 vdcsz5 6.015 0.661 2.561 evad15 5.875 0.754 2.654 vdcsz4 6.020 0.656 2.556 evad14 5.905 0.724 2.624 vdcsz3 6.036 0.640 2.540 evad13 5.818 0.811 2.711 vdcsz2 6.017 0.659 2.559 evad12 5.849 0.780 2.680 vdcsz1 5.983 0.693 2.593 evad11 5.830 0.799 2.699 vdcsz0 6.036 0.640 2.540 evad10 5.827 0.802 2.702 vdselpz 5.599 1.077 2.977 evad9 5.821 0.808 2.708 ided31 5.888 0.742 2.642 evad8 5.783 0.846 2.746 ided30 5.862 0.767 2.667 evad7 5.772 0.857 2.757 ided29 5.927 0.702 2.602 evad6 5.814 0.815 2.715 ided28 5.964 0.666 2.566 evad5 5.849 0.780 2.680 ided27 5.944 0.685 2.585 evad4 5.747 0.882 2.782 ided26 5.907 0.723 2.623 evad3 5.850 0.779 2.679 ided25 5.896 0.733 2.633 evad2 5.845 0.784 2.684 ided24 5.928 0.701 2.601 evad1 5.828 0.801 2.701 ided23 5.944 0.686 2.586 evad0 5.820 0.809 2.709 ided22 5.898 0.731 2.631 evlkrt 5.981 0.648 2.548 ided21 5.973 0.656 2.556 chapter 9 nb85et 169 design manual a13195ej5v0dm 9. 2 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in test program execution. failure to do this will result in the propagation of undefined values. chapter 9 nb85et 170 design manual a13195ej5v0dm 9. 3 pin functions (1/5) pin name i/o function vpa13 to vpa0 output address output for peripheral macro connected to npb vpd15 to vpd0 note i/o data i/o for peripheral macro connected to npb vpwrite output write access strobe output of signals vpd15 to vpd0 vpstb output data strobe output of signals vpd15 to vpd0 vplock output bus lock output vpubenz output upper byte enable output vpretr note input retry request input from peripheral macro connected to npb npb pins vpdact input retry function control input vareq input bus access right request input vaack output bus access right acknowledge output vba27 to vba0 note i/o address i/o for peripheral macro connected to vsb vbd31 to vbd0 note i/o data i/o for peripheral macro connected to vsb vbttyp1, vbttyp0 note i/o bus transfer type i/o vbstz note i/o transfer start i/o vbbenz3 to vbbenz0 note i/o byte enable i/o vbsize1, vbsize0 note i/o transfer size i/o vbwrite note i/o read/write status i/o vblock note i/o bus lock i/o vbctyp2 to vbctyp0 note i/o bus cycle status i/o vbseq2 to vbseq0 note i/o sequential status i/o vbbstr note i/o burst read status i/o vbwait note i/o wait response i/o vblast note i/o last response i/o vbahld note i/o address hold response i/o vbdc output data bus direction control output vdcsz7 to vdcsz0 note i/o chip select i/o vsb pins vdselpz note i/o peripheral i/o area access status i/o resetz input system reset input vbclk input internal system clock input clkb1 output internal system clock output cgrel input clock generator release input swstoprq output software stop mode request output to clock generator hwstoprq output hardware stop mode request output to clock generator stopz input hardware stop mode request input stprq output hardware/software stop mode request output to memc system control pins stpak input acknowledge input for input of stprq of memc note connected internally to the bus holder. chapter 9 nb85et 171 design manual a13195ej5v0dm (2/5) pin name i/o function idmastp input dma transfer terminate input dmarq3 to dmarq0 input dma transfer request input dmtco3 to dmtco0 output terminal count (dma transfer completed) output dmac pins dmactv3 to dmactv0 output dma acknowledge output nmi2 to nmi0 input non-maskable interrupt request (nmi) input intc pins int63 to int0 input maskable interrupt request input iroma19 to iroma2 output address output for rom iromz31 to iromz0 input data input for rom iromen output access enable output for rom iromwt input wait input for rom iromcs output iromia output vfb pins iromae output nec reserved pin (leave open) irama27 to irama2 output address output for ram iramz31 to iramz0 input data input for ram iraoz31 to iraoz0 output data output for ram iramen output access enable output for ram iramwr3 to iramwr0 output write enable output for ram iramrwb output read/write status output for ram vdb pins iramwt input wait input for ram ibdrrq input fetch request input from instruction cache ibea25 to ibea2 input fetch address input from instruction cache ibaack output address acknowledge output to instruction cache ibdrdy output data ready output to instruction cache ibdle3 to ibdle0 output data latch enable output to instruction cache ibedi31 to ibedi0 output data output to instruction cache iidrrq output fetch request output to instruction cache iiea25 to iiea2 output fetch address output to instruction cache iiaack input address acknowledge input from instruction cache iidlef input data latch enable input from instruction cache iiedi31 to iiedi0 input data input from instruction cache iibtft output branch target fetch status output to instruction cache iircan output code cancel status output to instruction cache bcunch output uncache status output to instruction cache instruction cache pins ibbtft input nec reserved pin (input a low level) chapter 9 nb85et 172 design manual a13195ej5v0dm (3/5) pin name i/o function iddarq output read/write access request output to data cache idaack output acknowledge output iddrrq input vsb read operation request input to bcu iddwrq input vsb write operation request input to bcu idseq4 input read/write operation type setting input idseq2 input read/write operation type setting input irrsa output vdb hold status output idretr output read retry request output idunch output uncache status output iddrdy output read data ready output idrrdy input read data ready input from data cache idhum input hit under miss-hit read input idea27 to idea0 input address input ided31 to ided0 note 1 i/o data i/o data cache pins ides output nec reserved pin note 2 eintlv6 to eintlv0 input interrupt type input from external intc eintrq input interrupt request input from external intc eintak output interrupt acknowledge output to external intc external intc pins eclrip output interrupt servicing end output to external intc dck input clock input for dcu dms input debug mode selection input ddi input debug data input ddo output debug data output drstz input reset input for dcu trcclk output trace clock output trcdata3 to trcdata0 output trace data output trcend output trace processing end output idbr2 to idbr0 output debug mode output evttrg output event trigger output dcresz output forcible reset output mwait input wait insertion control input dcwait output wait insertion control output dcu pins exhlt output halt mode status output notes 1. connected internally to the bus holder. 2. when using the data cache, always connect this pin to the ides pin of the data cache. leave open when unused. chapter 9 nb85et 173 design manual a13195ej5v0dm (4/5) pin name i/o function dbint input external debug interrupt input romtype input nec reserved pin (input a low level) ddoout output ddoenb output tapsm3 to tapsm0 output trg1, trg0 output dbresz output resmk output mskstp output msknmi2 to msknmi0 output mskhrq output dcu pins dbrdy output nec reserved pin (leave open) evastb input address strobe input evdstb input data strobe input evad15 to evad0 note i/o address/data i/o evien output evadn input enable output (n = 15 to 0) evoen output evadn output enable output (n = 15 to 0) evlkrt note i/o lock/retry i/o evirel input standby release input evclrip input ispr clear input evintak input interrupt acknowledge input evintrq output interrupt request output peripheral eva chip mode pins evintlv6 to evintlv0 output interrupt vector output ifirome input rom mapping enable input ifirob2 input location setting input of rom area ifira64 input ram area size selection input ifira32 input ram area size selection input ifira16 input ram area size selection input ifimaen input misalign access setting input ifid256 input data area setting input ifinsz1, ifinsz0 input vsb data bus size selection input operation mode setting pins ifiwrth input data cache write-back/write-through mode selection input note connected internally to the bus holder. chapter 9 nb85et 174 design manual a13195ej5v0dm (5/5) pin name i/o function ifiunch1 input data cache setting input ifiunch0 input instruction cache setting input pheva input peripheral eva chip mode setting input ifieva input external intc/internal intc selection input ifimode2 input ifirobe input ifiropr input ifirase input ifirabe input ifimode3 input ifiuswe input operation mode setting pins fcomb input nec reserved pin (input a low level) tbi39 to tbi0 input input test bus tbo34 to tbo0 output output test bus test input test bus control input bunri input normal/test mode selection input phtdo1, phtdo0 note input peripheral macro test input tesen output peripheral macro test enable output vptclk output clock output for peripheral macro test phtdin1, phtdin0 output peripheral macro test output vpresz output peripheral macro reset output phtest output peripheral test mode status output tmode1, tmode0 output test mode pins tbredz output nec reserved pin (leave open) note connected internally to the bus holder. chapter 9 nb85et 175 design manual a13195ej5v0dm 9. 4 electrical specifications (preliminary) the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 9. 4. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 9. 4. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 20.0 ns 9. 4. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode 0.5 0.6 ma/mhz i dd2 in halt mode (when dmac is not operating) 0.17 0.2 ma/mhz supply current i dd3 in stop mode 0 1.0 a remark the typ. value is a reference value for when t a = 25c, v dd = 3.3 v. chapter 9 nb85et 176 design manual a13195ej5v0dm 9. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) (1) clock timing parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 20.0 ns vbclk input high-level width <2> t kkh 10.0 ns vbclk input low-level width <3> t kkl 10.0 ns cpu operating frequency ? 050mhz (2) reset timing parameter symbol conditions min. max. unit resetz setup time (to vbclk )<4>t skr 2.3 ns resetz hold time (from vbclk )<5>t hkr 1.9 ns delay time from resetz to vpresz ? t drpr 0.9 3.2 ns vbclk (input) <1> <2> <3> vbclk (input) <5> <4> <5> <4> resetz (output) chapter 9 nb85et 177 design manual a13195ej5v0dm (3) vsb arbitration timing parameter symbol conditions min. max. unit vareq setup time (to vbclk )<6>t skq 0ns vareq hold time (from vbclk )<7>t hkq 3.4 ns delay time from vbclk to vaack <8> t dkk 2.0 5.4 ns vbclk (input) vareq (input) <7> <6> <8> vaack (output) vblock (output) vblock (external) bus master: nb85et hi-z hi-z bus master: external bus chapter 9 nb85et 178 design manual a13195ej5v0dm (4) vsb master read timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vbttyp <9> t dkt 1.8 7.0 ns vbttyp hold time (from vbclk ) <10> t hkt 3.2 ns delay time from vbclk to vba <11> t dka 2.0 7.8 ns delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp <12> t dks1 2.1 7.4 ns delay time from vbclk to vbbenz <13> t dks2 2.2 8.7 ns delay time from vbclk to vbseq, vblock <14> t dks3 2.3 8.2 ns delay time from vbclk to vdcsz, vdselpz <15> t dkc 2.3 8.0 ns delay time from vbclk to vbbstr <61> t dkbsr 2.1 6.6 ns vbd data setup time (to vbclk ) <16> t skd 0ns vbd data hold time (from vbclk ) <17> t hkd 2.8 ns vbwait, vbahld, vblast setup time (to vbclk ) <18> t skw 0.6 ns vbwait, vbahld, vblast hold time (from vbclk ) <19> t hkw 3.5 ns delay time from vbclk to vbdc <20> t dks4 2.2 6.1 ns chapter 9 nb85et 179 design manual a13195ej5v0dm (4) vsb master read timing (2/2) remarks 1. the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85et is driving. 2. rdy: when the vbwait, vbahld, and vblast signals are all low level wait: when the vbwait signal is high level, and the vbahld and vblast signals are low level vbclk (input) vbstz (output) vba27 to vba0 (output) <9> <10> <11> address3 vbsize1, vbsize0 <12> size1 size2 size3 size4 vbwrite (output) <12> vbbenz3 to vbbenz0 <13> byte en1 byte en3 byte en4 vbseq2 to vbseq0 <14> <14> vblock (output) vbctyp2 to vbctyp0 <12> ctyp1 ctyp2 ctyp3 ctyp4 vdcsz7 to vdcsz0 (output) vdselpz (output) <15> vbwait (input) vbahld (input) vblast (input) <20> vbttyp1, vbttyp0 seq seq seq seq seq <12> rdy wait rdy rdy rdy rdy d1 d2 d3 d4 vbd31 to vbd0 (input) <18> <16> <17> <19> vbdc (output) n_seq address1 address2 byte en2 address4 <61> vbbstr (output) (output) (output) (output) (output) (output) chapter 9 nb85et 180 design manual a13195ej5v0dm (5) vsb master write timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vbttyp <9> t dkt 1.8 7.0 ns vbttyp hold time (from vbclk ) <10> t hkt 3.2 ns delay time from vbclk to vba <11> t dka 2.0 8.0 ns delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp <12> t dks1 2.1 7.4 ns delay time from vbclk to vbbenz <13> t dks2 2.2 8.7 ns delay time from vbclk to vbseq, vblock <14> t dks3 2.3 8.2 ns delay time from vbclk to vdcsz, vdselpz <15> t dkc 2.3 8.0 ns vbwait, vbahld, vblast setup time (to vbclk ) <18> t skw 0.6 ns vbwait, vbahld, vblast hold time (from vbclk ) <19> t hkw 3.5 ns delay time from vbclk to vbdc <20> t dks4 2.2 6.2 ns delay time from vbclk to vbd data <21> t dkd0 1.9 6.3 ns delay time from vbclk <22> t dkd1 2.1 7.1 ns chapter 9 nb85et 181 design manual a13195ej5v0dm (5) vsb master write timing (2/2) remarks 1. the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85et is driving. 2. rdy: when the vbwait, vbahld, and vblast signals are all low level wait: when the vbwait signal is high level, and the vbahld and vblast signals are low level vbclk (input) vbstz (output) vba27 to vba0 (output) <9> <10> <11> address3 address4 vbsize1, vbsize0 (output) (output) (output) (output) <12> size1 size2 size3 size4 vbwrite (output) <12> vbbenz3 to vbbenz0 <13> byte en1 byte en3 byte en4 vbseq2 to vbseq0 <14> <14> vblock (output) vbctyp2 to vbctyp0 <12> ctyp1 ctyp2 ctyp3 ctyp4 vdcsz7 to vdcsz0 (output) vdselpz (output) <15> vbwait (input) vbahld (input) vblast (input) <20> vbttyp1, vbttyp0 (output) seq seq seq seq seq <12> rdy wait rdy rdy rdy rdy data1 vbd31 to vbd0 (output) <18> <21> <19> vbdc (output) n_seq address1 address2 byte en2 <22> data2 data3 data4 chapter 9 nb85et 182 design manual a13195ej5v0dm (6) npb read timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vpstb <23> t dkp 2.4 7.1 ns vpstb output high-level width <24> t ssh 60 ns vpstb output low-level width <25> t ssl 20 ns vpa address, vpwrite, vplock, vpubenz setup time (to vpstb ) <26> t ssa 20 ns vpa address, vpwrite, vplock, vpubenz hold time (from vpstb ) <27> t hsa 20 ns vpd read data setup time (to vpstb ) <28> t ssd 20 ns vpd read data hold time (from vpstb ) <29> t hsd 0ns vpretr setup time (to vpstb ) <30> t ssr 20 ns vpretr hold time (from vpstb ) <31> t hsr 0ns vpdact setup time (to vpstb ) <32> t ssc 20 ns vpdact hold time (from vpstb ) <33> t hsc 20 ns chapter 9 nb85et 183 design manual a13195ej5v0dm (6) npb read timing (2/2) remark the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85et is driving. <26> vbclk (input) vpstb (output) <24> <25> <26> <27> data <29> <28> <26> <26> <27> <31> <30> <32> <33> address vpa13 to vpa0 (output) vpwrite (output) vpd15 to vpd0 (input) vplock (output) vpubenz (output) vpretr (input) vpdact (input) <23> <27> <27> chapter 9 nb85et 184 design manual a13195ej5v0dm (7) npb write timing (1/2) parameter symbol conditions min. max. unit delay time from vbclk to vpstb <23> t dkp 2.4 7.1 ns vpstb output high-level width <24> t ssh 60 ns vpstb output low-level width <25> t ssl 20 ns vpa address, vpwrite, vplock, vpubenz setup time (to vpstb ) <26> t ssa 20 ns vpa address, vpwrite, vplock, vpubenz hold time (from vpstb ) <27> t hsa 20 ns vpd write data setup time (to vpstb ) <28> t ssd 20 ns vpd write data hold time (from vpstb ) <29> t hsd 20 ns vpretr setup time (to vpstb ) <30> t ssr 20 ns vpretr hold time (from vpstb ) <31> t hsr 0ns vpdact setup time (to vpstb ) <32> t ssc 20 ns vpdact hold time (from vpstb ) <33> t hsc 20 ns chapter 9 nb85et 185 design manual a13195ej5v0dm (7) npb write timing (2/2) remark the level of the broken line portion indicates the undefined state (weak unknown) in which the bus holder in the nb85et is driving. vbclk (input) vpstb (output) <24> <25> <26> <27> <26> <26> <26> <27> <32> <33> address vpa13 to vpa0 (output) vpwrite (output) vpd15 to vpd0 (output) vplock (output) vpubenz (output) vpretr (input) vpdact (input) <28> <29> data <31> <30> <23> <27> <27> chapter 9 nb85et 186 design manual a13195ej5v0dm (8) vfb access timing parameter symbol conditions min. max. unit delay time from vbclk to iromen <34> t dkroe 2.5 9.1 ns delay time from vbclk to iroma <35> t dkroa 2.6 13.7 ns iromz setup time (to vbclk ) <36> t skroz 3.3 ns iromz hold time (from vbclk ) <37> t hkroz 3.2 ns note hold data during the iromen signal is low level. vbclk (input) iromen (output) address1 iroma19 to iroma2 (output) iromz31 to iromz0 (input) note data1 <36> data2 data3 <37> <34> <35> hold address2 address3 chapter 9 nb85et 187 design manual a13195ej5v0dm (9) vdb read timing parameter symbol conditions min. max. unit delay time from vbclk to iramrwb <38> t dkrar 2.5 9.7 ns delay time from vbclk to iramen <39> t dkrae 2.2 10.4 ns delay time from vbclk to irama <40> t dkraa 2.7 10.2 ns iramz setup time (to vbclk ) <41> t skraz 4.6 ns iramz hold time (from vbclk ) <42> t hkraz 3.8 ns note do not make signals iramz31 to iramz0 high impedance. vbclk (input) iramrwb (output) address1 irama27 to irama2 (output) iramz31 to iramz0 (input) note address2 address3 data1 <41> iramen (output) data2 data3 <42> <39> <38> <40> chapter 9 nb85et 188 design manual a13195ej5v0dm (10) vdb write timing parameter symbol conditions min. max. unit delay time from vbclk to iramwr <43> t dkraw 2.6 10.2 ns delay time from vbclk to iraoz <44> t dkraz 2.5 10.2 ns note signals iraoz31 to iraoz0 are always output and do not become high impedance. write operations are controlled by the iramen signal and signals iramwr3 to iramwr0. data cannot be written when the iramen signal is low level. vbclk (input) iramrwb (output) address1 irama27 to irama2 (output) address2 address3 iramen (output) iraoz31 to iraoz0 (output) note iramwr3 to iramwr0 (output) <43> we1 we2 we3 <44> data1 data2 data3 chapter 9 nb85et 189 design manual a13195ej5v0dm (11) dma transfer request, transfer completion timing parameter symbol conditions min. max. unit dmarq setup time (to vbclk ) <45> t skdq 0ns dmarq hold time (from vbclk ) <46> t hkdq 2.3 ns delay time from vbclk to dmactv, dmtco <47> t dkdc 2.1 6.5 ns note in order to avoid the generation of the next cycle, make the dmarqn signal low level in this cycle. remark n = 3 to 0 (12) dma transfer abort timing parameter symbol conditions min. max. unit idmastp setup time (to vbclk ) <48> t skds 3.5 ns idmastp hold time (from vbclk ) <49> t hkds 2.9 ns note input an active level (high level) of 1 clock or more. vbclk (input) dmactvn (output) dmarqn (input) <45> <46> note <47> <47> dmtcon (output) <45> vbclk (input) idmastp (input) note <49> <48> chapter 9 nb85et 190 design manual a13195ej5v0dm (13) software stop mode timing parameter symbol conditions min. max. unit delay time from vbclk to stprq <50> t dksq 2.2 6.1 ns stpak setup time (to vbclk ) <51> t sksa 1.0 ns stpak hold time (from stprq ) <52> t hqsa 9.6 ns delay time from vbclk to swstoprq <53> t dkss 2.1 5.7 ns delay time from int, nmi to swstoprq <54> t drsr 0 20.8 ns cgrel setup time (to vbclk ) <55> t sksg 0ns cgrel hold time (from vbclk ) <56> t hksg 3.2 ns notes 1. software stop mode is released upon detection of the rising edge of these signals. 2. input an active level (high level) of 1 clock or more. vbclk (input) stprq (output) <50> <50> <51> <52> <53> <54> <56> stpak (input) swstoprq (output) int63 to int0 (input) note 1 nmi2 to nmi0 (input) note 1 cgrel (input) note 2 <55> chapter 9 nb85et 191 design manual a13195ej5v0dm (14) hardware stop mode timing parameter symbol conditions min. max. unit delay time from vbclk to stprq <50> t dksq 2.2 6.1 ns stpak setup time (to vbclk ) <51> t sksa 1.0 ns stpak hold time (from stprq ) <52> t hqsa 9.6 ns delay time from vbclk to hwstoprq <53> t dkss 2.2 5.9 ns delay time from stopz to hwstoprq <54> t drsr 0 20.8 ns cgrel setup time (to vbclk ) <55> t sksg 0ns cgrel hold time (from vbclk ) <56> t hksg 3.2 ns stopz setup time (to vbclk ) <57> t skst 0ns notes 1. hardware stop mode is released upon detection of the rising edge of this signal. 2. input an active level (high level) of 1 clock or more. vbclk (input) stprq (output) <50> <50> <51> <52> <53> <54> <56> stpak (input) hwstoprq (output) stopz (input) note 1 cgrel (input) note 2 <57> <55> chapter 9 nb85et 192 design manual a13195ej5v0dm (15) interrupt timing parameter symbol conditions min. max. unit int, nmi high-level width <58> t wih 5.0 ns int, nmi low-level width <59> t wil 5.0 ns int, nmi interval time <60> t cyi 3 t cyk ns note an interrupt is generated upon detection of the rising edge of these signals. int63 to int0 (input) note nmi2 to nmi0 (input) note <58> <59> <60> chapter 9 nb85et 193 design manual a13195ej5v0dm (16) dcu timing (a) dck input timing parameter symbol conditions min. max. unit dck input cycle <62> t cyd 30.0 ns dck input high-level width <63> t ddh 10.0 ns dck input low-level width <64> t ddl 10.0 ns dck rise time <65> t dr 5.0 ns dck fall time <66> t df 5.0 ns (b) ddi, dms, ddo timing parameter symbol conditions min. max. unit ddi, dms setup time (to dck ) <67> t sdtd 7.0 ns ddi, dms hold time (from dck ) <68> t hddt 3.0 ns delay time from dck to ddo <69> t dddt 2.0 10.0 ns 0.5 v dd 0.8 v dd 0.2 v dd dck (input) <63> <62> <64> <66> <65> dck (input) <67> ddi (input) dms (input) ddo (output) <69> <68> 194 design manual a13195ej5v0dm chapter 10 nb85e500 (under development) the nb85e500 is used as follows according to the type of external memory that is connected. target cpu core types of connected external memory memory controller (memc) sram, rom, page rom, flash memory nb85e500 nb85e, nb85et sdram nb85e500 + nu85e502 remark for details of the nu85e502, refer to chapter 12 nu85e502 . 10. 1 outline the nb85e500 is a basic core macro used to control external memory. it features on chip sram, and i/o controller, and a page rom controller. the nb85e500 can be used to start the external bus cycle when it is connected to the nb85e (or nb85et) via vsb. it can also be used to control sdram by connecting an sdram controller (nu85e502) to the nb85e500. 10. 1. 1 symbol diagram number of grids 34.0k grids 96.9k grids (including wiring area) number of separation simulation patterns 14.3k chapter 10 nb85e500 195 design manual a13195ej5v0dm vptclk in phtest in out phtdo (1:0) csz (7:0) astbz dstbz mpxcz rdcyz busst benz (3:0) refrqz selfref bcystz sdclk stprq stpak mce mpxen bcpen a (25:0) rdz wrz (3:0) iordz iowrz waitz hldrqz hldakz dc (3:0) d (31:0) vbttyp (1:0) vbd (31:0) vpresz vbahld vblast vbseq (2:0) vbwrite vbstz vareq vpstb vpubenz vpwrite vaack vblock vdselpz vpd (15:0) vbwait vbbstr vpa (13:0) vba (25:0) vbbenz (3:0) vbctyp (2:0) vdcsz (7:0) vbclk out out out out out out out out in out out in out in in in out in/out out out out out in in out out in in in in out out out out out out out in out in/out in/out in in/out in in/out in in/out in in/out in out out in in in in in in in in out out out out out out out out out out out out in in in in in in out out out out out out out in in in out in in in in in in out out out out out out in out out phtdin (1:0) in ct502i5 (1:0) ctcso0 (4:0) ctlo (1:0) ctcsi7 (3:0) ctcsi6 (3:0) ctcsi5 (3:0) ctcsi4 (3:0) ctcsi3 (3:0) ctcsi2 (3:0) ctcsi1 (3:0) ctcsi0 (3:0) ctcso7 (4:0) ctcso6 (4:0) ctcso5 (4:0) ctcso4 (4:0) ctcso3 (4:0) ctcso2 (4:0) ctcso1 (4:0) ct501o0 (3:0) ct501o1 (3:0) ct501o7 (3:0) ct501i0 (2:0) ct501i3 (2:0) ct501i4 (2:0) ct501i6 (2:0) ct501i7 (2:0) mten ct501i5 (2:0) ct501i2 (2:0) ct501i1 (2:0) ct501o6 (3:0) ct501o5 (3:0) ct501o4 (3:0) ct501o3 (3:0) ct501o2 (3:0) ct502i0 (1:0) ct502o7 (1:0) bcp pisl ctl501 ct502i6 (1:0) ct502i4 (1:0) ct502i3 (1:0) ct502i2 (1:0) ct502i1 (1:0) rwc (7:0) ct502i7 (1:0) ct502o6 (1:0) ct502o5 (1:0) ct502o4 (1:0) ct502o3 (1:0) ct502o2 (1:0) ct502o1 (1:0) ct502o0 (1:0) chapter 10 nb85e500 196 design manual a13195ej5v0dm 10. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins (1/2) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) vbclk 0.029 1.929 vpstb 0.009 1.909 vba25 0.081 1.981 vpubenz 0.011 1.911 vba24 0.064 1.964 vpa13 0.035 1.935 vba23 0.063 1.963 vpa12 0.036 1.936 vba22 0.065 1.965 vpa11 0.034 1.934 vba21 0.071 1.971 vpa10 0.045 1.945 vba20 0.099 1.999 vpa9 0.035 1.935 vba19 0.061 1.961 vpa8 0.013 1.913 vba18 0.155 2.055 vpa7 0.052 1.952 vba17 0.062 1.962 vpa6 0.043 1.943 vba16 0.063 1.963 vpa5 0.046 1.946 vba15 0.102 2.002 vpa4 0.008 1.908 vba14 0.107 2.007 vpa3 0.008 1.908 vba13 0.076 1.976 vpa2 0.061 1.961 vba12 0.087 1.987 vpa1 0.012 1.912 vba11 0.112 2.012 vpa0 0.075 1.975 vba10 0.122 2.022 vpwrite 0.013 1.913 vba9 0.068 1.968 stprq 0.182 2.082 vba8 0.091 1.991 mce 0.137 2.037 vba7 0.069 1.969 bcpen 0.131 2.031 vba6 0.096 1.996 waitz 0.151 2.051 vba5 0.075 1.975 hldrqz 0.135 2.035 vba4 0.068 1.968 selfref 0.162 2.062 vba3 0.075 1.975 ctcsi73 0.043 1.943 vba2 0.070 1.970 ctcsi72 0.041 1.941 vba1 0.107 2.007 ctcsi71 0.042 1.942 vba0 0.070 1.970 ctcsi70 0.178 2.078 vbctyp2 0.025 1.925 ctcsi63 0.149 2.049 vbctyp1 0.036 1.936 ctcsi62 0.067 1.967 vbctyp0 0.049 1.949 ctcsi61 0.136 2.036 vpresz 0.011 1.911 ctcsi60 0.232 2.132 vbseq2 0.100 2.000 ctcsi53 0.110 2.010 vbseq1 0.092 1.992 ctcsi52 0.105 2.005 vbseq0 0.085 1.985 ctcsi51 0.069 1.969 vaack 0.146 2.046 ctcsi50 0.126 2.026 chapter 10 nb85e500 197 design manual a13195ej5v0dm (1) input pins (2/2) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) ctcsi43 0.069 1.969 ct502i10 0.224 2.124 ctcsi42 0.064 1.964 ct502i01 0.079 1.979 ctcsi41 0.150 2.050 ct502i00 0.090 1.990 ctcsi40 0.199 2.099 phtest 0.016 1.916 ctcsi33 0.119 2.019 phtdin1 0.014 1.914 ctcsi32 0.073 1.973 phtdin0 0.028 1.928 ctcsi31 0.156 2.056 vptclk 0.176 2.076 ctcsi30 0.081 1.981 mpxen 0.166 2.066 ctcsi23 0.079 1.979 ct501i72 0.111 2.011 ctcsi22 0.067 1.967 ct501i71 0.025 1.925 ctcsi21 0.132 2.032 ct501i70 0.214 2.114 ctcsi20 0.350 2.250 ct501i62 0.093 1.993 ctcsi13 0.168 2.068 ct501i61 0.171 2.071 ctcsi12 0.054 1.954 ct501i60 0.044 1.944 ctcsi11 0.146 2.046 ct501i52 0.180 2.080 ctcsi10 0.080 1.980 ct501i51 0.058 1.958 ctcsi03 0.134 2.034 ct501i50 0.298 2.198 ctcsi02 0.046 1.946 ct501i42 0.044 1.944 ctcsi01 0.109 2.009 ct501i41 0.140 2.040 ctcsi00 0.045 1.945 ct501i40 0.073 1.973 ct502i71 0.043 1.943 ct501i32 0.051 1.951 ct502i70 0.105 2.005 ct501i31 0.053 1.953 ct502i61 0.216 2.116 ct501i30 0.057 1.957 ct502i60 0.201 2.101 ct501i22 0.208 2.108 ct502i51 0.092 1.992 ct501i21 0.048 1.948 ct502i50 0.125 2.025 ct501i20 0.196 2.096 ct502i41 0.061 1.961 ct501i12 0.074 1.974 ct502i40 0.270 2.170 ct501i11 0.209 2.109 ct502i31 0.242 2.142 ct501i10 0.131 2.031 ct502i30 0.231 2.131 ct501i02 0.286 2.186 ct502i21 0.062 1.962 ct501i01 0.056 1.956 ct502i20 0.070 1.970 ct501i00 0.175 2.075 ct502i11 0.112 2.012 chapter 10 nb85e500 198 design manual a13195ej5v0dm (2) output pins (1/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vareq 13.311 ?? wrz1 13.298 ?? vblock 6.565 0.063 1.963 wrz0 13.300 ?? vbttyp1 6.580 0.049 1.949 iordz 13.314 ?? vbttyp0 6.580 0.048 1.948 iowrz 13.323 ?? vbbstr 6.569 0.059 1.959 hldakz 13.289 ?? vdselpz 6.574 0.055 1.955 dc3 13.043 ?? vbwait 6.526 0.102 2.002 dc2 13.067 ?? vbahld 6.527 0.102 2.002 dc1 13.062 ?? vblast 6.524 0.104 2.004 dc0 13.070 ?? stpak 13.276 ?? csz7 13.338 ?? a25 13.055 ?? csz6 13.326 ?? a24 13.047 ?? csz5 13.337 ?? a23 13.001 ?? csz4 13.324 ?? a22 13.053 ?? csz3 13.333 ?? a21 13.052 ?? csz2 13.337 ?? a20 13.068 ?? csz1 13.328 ?? a19 13.060 ?? csz0 13.335 ?? a18 13.049 ?? benz3 13.043 ?? a17 13.051 ?? benz2 13.047 ?? a16 13.051 ?? benz1 13.048 ?? a15 13.057 ?? benz0 13.043 ?? a14 13.049 ?? bcystz 13.035 ?? a13 13.024 ?? refrqz 13.296 ?? a12 13.058 ?? sdclk 13.066 ?? a11 13.047 ?? ctcso74 13.067 ?? a10 13.066 ?? ctcso73 13.064 ?? a9 13.052 ?? ctcso72 13.271 ?? a8 13.063 ?? ctcso71 13.067 ?? a7 13.053 ?? ctcso70 13.068 ?? a6 13.051 ?? ctcso64 13.059 ?? a5 13.034 ?? ctcso63 13.063 ?? a4 13.029 ?? ctcso62 13.064 ?? a3 13.049 ?? ctcso61 13.068 ?? a2 13.044 ?? ctcso60 13.061 ?? a1 13.054 ?? ctcso54 13.039 ?? a0 13.055 ?? ctcso53 13.051 ?? rdz 13.012 ?? ctcso52 13.237 ?? wrz3 13.280 ?? ctcso51 13.034 ?? wrz2 13.326 ?? ctcso50 13.037 ?? chapter 10 nb85e500 199 design manual a13195ej5v0dm (2) output pins (2/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) ctcso44 13.056 ?? ct502o11 12.972 ?? ctcso43 13.063 ?? ct502o10 13.061 ?? ctcso42 13.314 ?? ct502o01 13.026 ?? ctcso41 13.048 ?? ct502o00 13.035 ?? ctcso40 13.056 ?? phtdo1 3.248 ?? ctcso34 12.963 ?? phtdo0 3.296 ?? ctcso33 12.867 ?? astbz 13.049 ?? ctcso32 13.335 ?? dstbz 13.332 ?? ctcso31 13.015 ?? mpxcz 13.329 ?? ctcso30 12.959 ?? rdcyz 13.068 ?? ctcso24 13.043 ?? busst 13.316 ?? ctcso23 13.069 ?? ct501o73 13.064 ?? ctcso22 13.311 ?? ct501o72 13.330 ?? ctcso21 13.063 ?? ct501o71 12.967 ?? ctcso20 13.068 ?? ct501o70 12.952 ?? ctcso14 13.065 ?? ct501o63 13.039 ?? ctcso13 13.063 ?? ct501o62 13.065 ?? ctcso12 13.233 ?? ct501o61 13.056 ?? ctcso11 13.063 ?? ct501o60 13.058 ?? ctcso10 12.910 ?? ct501o53 13.334 ?? ctcso04 13.030 ?? ct501o52 13.065 ?? ctcso03 13.022 ?? ct501o51 13.061 ?? ctcso02 13.300 ?? ct501o50 12.990 ?? ctcso01 13.040 ?? ct501o43 13.264 ?? ctcso00 13.041 ?? ct501o42 13.140 ?? ctlo1 13.326 ?? ct501o41 13.062 ?? ctlo0 13.062 ?? ct501o40 13.067 ?? mten 12.950 ?? ct501o33 13.056 ?? ct502o71 13.070 ?? ct501o32 12.893 ?? ct502o70 13.062 ?? ct501o31 13.056 ?? ct502o61 13.067 ?? ct501o30 13.065 ?? ct502o60 12.944 ?? ct501o23 13.028 ?? ct502o51 13.012 ?? ct501o22 13.021 ?? ct502o50 13.065 ?? ct501o21 12.984 ?? ct502o41 13.057 ?? ct501o20 12.970 ?? ct502o40 12.925 ?? ct501o13 13.176 ?? ct502o31 13.046 ?? ct501o12 13.210 ?? ct502o30 13.054 ?? ct501o11 13.061 ?? ct502o21 12.934 ?? ct501o10 13.060 ?? ct502o20 12.999 ?? ct501o03 13.064 ?? chapter 10 nb85e500 200 design manual a13195ej5v0dm (2) output pins (3/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) ct501o10 13.060 ?? rwc7 12.959 ?? ct501o03 13.064 ?? rwc6 12.992 ?? ct501o02 13.319 ?? rwc5 13.062 ?? ct501o01 13.038 ?? rwc4 13.009 ?? ct501o00 13.029 ?? rwc3 12.929 ?? bcp 13.046 ?? rwc2 13.060 ?? pisl 13.063 ?? rwc1 13.062 ?? ctl501 12.941 ?? rwc0 13.067 ?? (3) i/o pins (1/2) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vdcsz7 6.313 0.315 2.215 vbd16 6.459 0.170 2.070 vdcsz6 6.282 0.347 2.247 vbd15 6.509 0.120 2.020 vdcsz5 6.263 0.365 2.265 vbd14 6.500 0.128 2.028 vdcsz4 6.226 0.403 2.303 vbd13 6.509 0.120 2.020 vdcsz3 6.312 0.316 2.216 vbd12 6.473 0.155 2.055 vdcsz2 6.233 0.395 2.295 vbd11 6.407 0.221 2.121 vdcsz1 6.207 0.421 2.321 vbd10 6.420 0.209 2.109 vdcsz0 6.294 0.335 2.235 vbd9 6.509 0.120 2.020 vbbenz3 6.494 0.135 2.035 vbd8 6.474 0.155 2.055 vbbenz2 6.496 0.132 2.032 vbd7 6.459 0.170 2.070 vbbenz1 6.502 0.126 3.026 vbd6 6.488 0.140 2.040 vbbenz0 6.488 0.141 2.041 vbd5 6.460 0.169 2.069 vbd31 6.509 0.120 2.020 vbd4 6.489 0.140 2.040 vbd30 6.512 0.117 2.017 vbd3 6.487 0.142 2.042 vbd29 6.519 0.110 2.010 vbd2 6.511 0.117 2.017 vbd28 6.469 0.160 2.060 vbd1 6.457 0.171 2.071 vbd27 6.508 0.121 2.021 vbd0 6.452 0.177 2.077 vbd26 6.510 0.119 2.019 vbwrite 6.455 0.173 2.073 vbd25 6.506 0.123 2.023 vbstz 6.389 0.240 2.140 vbd24 6.450 0.179 2.079 vpd15 6.564 0.111 2.011 vbd23 6.490 0.139 2.039 vpd14 6.492 0.183 2.083 vbd22 6.481 0.147 2.047 vpd13 6.487 0.188 2.088 vbd21 6.485 0.144 2.044 vpd12 6.528 0.147 2.047 vbd20 6.486 0.142 2.042 vpd11 6.548 0.127 2.027 vbd19 6.436 0.193 2.093 vpd10 6.555 0.120 2.020 vbd18 6.477 0.151 2.051 vpd9 6.545 0.130 2.030 vbd17 6.465 0.164 2.064 vpd8 6.535 0.140 2.040 chapter 10 nb85e500 201 design manual a13195ej5v0dm (3) i/o pins (2/2) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vpd7 6.522 0.199 2.099 d19 6.483 0.146 2.046 vpd6 6.552 0.169 2.069 d18 6.455 0.173 2.073 vpd5 6.548 0.173 2.073 d17 6.463 0.166 2.066 vpd4 6.529 0.192 2.092 d16 6.458 0.171 2.071 vpd3 6.509 0.212 2.112 d15 6.423 0.206 2.106 vpd2 6.473 0.248 2.148 d14 6.436 0.193 2.093 vpd1 6.467 0.255 2.155 d13 6.410 0.219 2.119 vpd0 6.479 0.242 2.142 d12 6.454 0.175 2.075 d31 6.433 0.196 2.096 d11 6.505 0.124 2.024 d30 6.393 0.235 2.135 d10 6.474 0.155 2.055 d29 6.414 0.214 2.114 d9 6.423 0.205 2.105 d28 6.452 0.177 2.077 d8 6.440 0.189 2.089 d27 6.427 0.201 2.101 d7 6.449 0.180 2.080 d26 6.421 0.208 2.108 d6 6.417 0.212 2.112 d25 6.435 0.194 2.094 d5 6.463 0.166 2.066 d24 6.437 0.192 2.092 d4 6.431 0.197 2.097 d23 6.436 0.193 2.093 d3 6.393 0.236 2.136 d22 6.450 0.179 2.079 d2 6.361 0.267 2.167 d21 6.439 0.189 2.089 d1 6.472 0.156 2.056 d20 6.443 0.185 2.085 d0 6.472 0.157 2.057 10. 2 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in the test program. failure to this so will result in the propagation of undefined values. chapter 10 nb85e500 202 design manual a13195ej5v0dm 10. 3 pin functions (1/3) pin name i/o function vbclk input internal system clock input vdcsz7 to vdcsz0 i/o chip select i/o vba25 to vba0 input address input vbbenz3 to vbbenz0 i/o byte enable i/o vbctyp2 to vbctyp0 input bus cycle status input vbd31 to vbd0 i/o data i/o vpresz input reset input vbseq2 to vbseq0 input sequential status input vbwrite i/o read/write status i/o vbstz i/o transfer start i/o vareq output bus access right request output vaack input bus access right acknowledge input vblock output bus lock output vbttyp1, vbttyp0 output bus transfer type output vbbstr output burst read status output vdselpz output peripheral i/o area access status output vbwait output wait response output vbahld output address hold response output vblast output last response output vpstb input data strobe input (for npb) vpubenz input upper byte enable input (for npb) vpa13 to vpa0 input address input (for npb) vpwrite input write access strobe input (for npb) vpd15 to vpd0 i/o data i/o (for npb) stprq input stop mode request input nb85e/nb85et connection pins stpak output acknowledge output for stprq input mce input men bit reset value control input for bct register (n = 0 to 7) initial setting pins bcpen input bcp bit reset value control input for bcp register a25 to a0 output external memory address output d31 to d0 i/o external memory data i/o rdz output sram/page rom read strobe output wrz3 to wrz0 output sram/page rom write strobe output iordz output external i/o read strobe output iowrz output external i/o write strobe output waitz input wait request input hldrqz input external bus hold request input external memory connection pins hldakz output external bus hold request acknowledge output chapter 10 nb85e500 203 design manual a13195ej5v0dm (2/3) pin name i/o function dc3 to dc0 output data bus control output csz7 to csz0 output chip select output benz3 to benz0 output byte enable output bcystz output bus cycle start status output refrqz output refresh status output selfref input self refresh request input external memory connection pins sdclk output sdram sync clock output ctcsi73 to ctcsi70 input control input from nu85e502 (for cs7 area) ctcsi63 to ctcsi60 input control input from nu85e502 (for cs6 area) ctcsi53 to ctcsi50 input control input from nu85e502 (for cs5 area) ctcsi43 to ctcsi40 input control input from nu85e502 (for cs4 area) ctcsi33 to ctcsi30 input control input from nu85e502 (for cs3 area) ctcsi23 to ctcsi20 input control input from nu85e502 (for cs2 area) ctcsi13 to ctcsi10 input control input from nu85e502 (for cs1 area) ctcsi03 to ctcsi00 input control input from nu85e502 (for cs0 area) ctcso74 to ctcso70 output control output to nu85e502 (for cs7 area) ctcso64 to ctcso60 output control output to nu85e502 (for cs6 area) ctcso54 to ctcso50 output control output to nu85e502 (for cs5 area) ctcso44 to ctcso40 output control output to nu85e502 (for cs4 area) ctcso34 to ctcso30 output control output to nu85e502 (for cs3 area) ctcso24 to ctso20 output control output to nu85e502 (for cs2 area) ctcso14 to ctcso10 output control output to nu85e502 (for cs1 area) ctcso04 to ctcso00 output control output to nu85e502 (for cs0 area) ctlo1, ctlo0 output control output to nu85e502 mten output test mode enable output to nu85e502 ct502i71, ct502i70 input control input from nu85e502 (for cs7 area) ct502i61, ct502i60 input control input from nu85e502 (for cs6 area) ct502i51, ct502i50 input control input from nu85e502 (for cs5 area) ct502i41, ct502i40 input control input from nu85e502 (for cs4 area) ct502i31, ct502i30 input control input from nu85e502 (for cs3 area) ct502i21, ct502i20 input control input from nu85e502 (for cs2 area) ct502i11, ct502i10 input control input from nu85e502 (for cs1 area) ct502i01, ct502i00 input control input from nu85e502 (for cs0 area) ct502o71, ct502o70 output control output to nu85e502 (for cs7 area) ct502o61, ct502o60 output control output to nu85e502 (for cs6 area) ct502o51, ct502o50 output control output to nu85e502 (for cs5 area) nu85e502 connection pins ct502o41, ct502o40 output control output to nu85e502 (for cs4 area) chapter 10 nb85e500 204 design manual a13195ej5v0dm (3/3) pin name i/o function ct502o31, ct502o30 output control output to nu85e502 (for cs3 area) ct502o21, ct502o20 output control output to nu85e502 (for cs2 area) ct502o11, ct502o10 output control output to nu85e502 (for cs1 area) nu85e502 connection pins ct502o01, ct502o00 output control output to nu85e502 (for cs0 area) phtest input peripheral test mode status input phtdin1, phtdin0 input peripheral macro test input phtdo1, phtdo0 output peripheral macro test output test mode pins vptclk input test clock input mpxen input nec reserved pin (input a low level) astbz output nec reserved pin (leave open) dstbz output nec reserved pin (leave open) mpxcz output nec reserved pin (leave open) rdcyz output nec reserved pin (leave open) busst output nec reserved pin (leave open) ct501i72 to ct501i70 input nec reserved pin (input a low level) ct501i62 to ct501i60 input nec reserved pin (input a low level) ct501i52 to ct501i50 input nec reserved pin (input a low level) ct501i42 to ct501i40 input nec reserved pin (input a low level) ct501i32 to ct501i30 input nec reserved pin (input a low level) ct501i22 to ct501i20 input nec reserved pin (input a low level) ct501i12 to ct501i10 input nec reserved pin (input a low level) ct501i02 to ct501i00 input nec reserved pin (input a low level) ct501o73 to ct501o70 output nec reserved pin (leave open) ct501o63 to ct501o60 output nec reserved pin (leave open) ct501o53 to ct501o50 output nec reserved pin (leave open) ct501o43 to ct501o40 output nec reserved pin (leave open) ct501o33 to ct501o30 output nec reserved pin (leave open) ct501o23 to ct501o20 output nec reserved pin (leave open) ct501o13 to ct501o10 output nec reserved pin (leave open) ct501o03 to ct501o00 output nec reserved pin (leave open) bcp output nec reserved pin (leave open) pisl output nec reserved pin (leave open) ctl501 output nec reserved pin (leave open) nec reserved pins rwc7 to rwc0 output nec reserved pin (leave open) chapter 10 nb85e500 205 design manual a13195ej5v0dm 10. 4 electrical specifications (preliminary) the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 10. 4. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 10. 4. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 15.0 ns 10. 4. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode 0.18 0.27 ma/mhz supply current i dd2 in stop mode 0 1.0 a remarks 1. the above supply current value is a reference value calculated from the number of grids. 2. the typ. value is a reference value for when t a = 25 c, v dd = 3.3 v. chapter 10 nb85e500 206 design manual a13195ej5v0dm 10. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) (1) sram/page rom read timing (1/3) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time from vbclk to address <2> t ad t dka + 0.4 note t dka + 2.5 note ns delay time from vbclk to csz <3> t cszd1 t dkc + 0.5 note t dkc + 2.5 note ns delay time from vbclk to rdz <4> t rdzd1 1.5 5.4 ns delay time from vbclk to rdz <5> t rdzd2 1.5 5.0 ns data setup time (to vbclk )<6>t ds1 0ns data hold time (from vbclk )<7>t dh1 1.0 ns delay time from vbclk to bcystz <8> t bcyd 1.6 t dks1 + 1.7 note ns waitz setup time (to vbclk )<9>t wts 0ns waitz hold time (from vbclk ) <10> t wth 0.9 ns delay time from vbclk to vbwait, vbahld, vblast <11> t vrd1 5.6 ns delay time from vbclk to vbwait, vbahld, vblast <12> t vrd2 1.2 ns delay time from vbclk to vbd <13> t vbd1 6.5 ns delay time from vbclk to vbd <14> t vbd2 1.7 ns delay time from vbclk to dc <15> t dcd1 t dks1 + 0.7 note t dks1 + 3.1 note ns note t dka : delay time from vbclk to vba t dkc : delay time from vbclk to vdcsz, vdselpz t dks1 : delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp the above are the electrical specifications of the nb85e (or nb85et). refer to section 7. 4. 4 ac characteristics (or 9. 4. 4 ac characteristics ). chapter 10 nb85e500 207 design manual a13195ej5v0dm (1) sram/page rom read timing (2/3) (a) when wait is inserted remarks 1. t1, t2: basic state in which nb85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) ti: idle state inserted by setting bus cycle control register (bcc) 2. the level of the broken line portion of the vbwait, vbahld, vblast, and vbd31 to vbd0 signals indicates the undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. vbclk (input) a25 to a0 (output) t1 t2 csz7 to csz0 (output) rdz (output) d31 to d0 (input) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) vbd31 to vbd0 (output) dc3 to dc0 (output) t1 tw1 t2 ti <2> <4> <1> <5> <7> <6> <8> <10> <9> <11> <12> <13> <14> <15> <8> <4> <5> <7> <6> <8> <8> <10> <9> <13> <14> <2> hi-z hi-z hi-z <3> <3> chapter 10 nb85e500 208 design manual a13195ej5v0dm (1) sram/page rom read timing (3/3) (b) when address setting wait is inserted remarks 1. t1, t2: basic state in which nb85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) tw2: wait state through waitz pin input ta: address setting wait state inserted by setting the address setting wait control register (asc) 2. the level of the broken line portion of the vbwait, vbahld, vblast, and vbd31 to vbd0 signals indicates the undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. vbclk (input) a25 to a0 (output) t1 tw1 csz7 to csz0 (output) rdz (output) d31 to d0 (input) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) vbd31 to vbd0 (output) dc3 to dc0 (output) tw2 t2 ta t1 t2 <2> <1> <2> <4> <5> <4> <7> <6> <8> <10> <9> <11> <12> <15> <8> <8> <8> <10> <9> <13> <14> <10> <9> hi-z hi-z <3> <3> chapter 10 nb85e500 209 design manual a13195ej5v0dm (2) sram write timing (1/3) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time from vbclk to address <2> t ad t dka + 0.4 note t dka + 2.5 note ns delay time from vbclk to csz <3> t cszd1 t dkc + 0.5 note t dkc + 2.5 note ns delay time from vbclk to bcystz <8> t bcyd 1.6 t dks1 + 1.7 note ns waitz setup time (to vbclk )<9>t wts 0ns waitz hold time (from vbclk ) <10> t wth 0.9 ns delay time from vbclk to vbwait, vbahld, vblast <11> t vrd1 5.6 ns delay time from vbclk to vbwait, vbahld, vblast <12> t vrd2 1.2 ns delay time from vbclk to dc <16> t dcd2 1.8 6.0 ns delay time from vbclk to wrz <17> t wrzd 1.6 4.9 ns delay time from vbclk to data <18> t dd1 t dkd1 + 0.4 note t dkd1 + 2.0 note ns delay time from vbclk to data <19> t dd2 t dkd0 + 0.4 note t dkd0 + 2.0 note ns delay time from vbbenz to benz ? t bnzd 0.4 1.8 ns note t dka : delay time from vbclk to vba t dkc : delay time from vbclk to vdcsz, vdselpz t dks1 : delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp t dkd1 : delay time from vbclk to vbd data t dkd0 : delay time from vbclk to vbd data the above are the electrical specifications of the nb85e (or nb85et). refer to section 7. 4. 4 ac characteristics (or 9. 4. 4 ac characteristics ). chapter 10 nb85e500 210 design manual a13195ej5v0dm (2) sram write timing (2/3) (a) when wait is inserted remarks 1. t1, t2: basic state in which nb85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) ti: idle state inserted by setting bus cycle control register (bcc) 2. the level of the broken line portion of the d31 to d0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, and vblast signals indicates undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. vbclk (input) a25 to a0 (output) csz7 to csz0 (output) wrz3 to wrz0 (output) d31 to d0 (output) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) dc3 to dc0 (output) t1 t2 t1 tw1 t2 ti <2> <1> <2> <17> <17> <17> <17> <18> <8> <8> <8> <8> <9> <10> <9> <10> <11> <12> <16> <3> <3> <19> <19> invalid chapter 10 nb85e500 211 design manual a13195ej5v0dm (2) sram write timing (3/3) (b) when address setting wait is inserted remarks 1. t1, t2: basic state in which nb85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) tw2: wait state through waitz pin input ta: address setting wait state inserted by setting the address setting wait control register (asc) 2. the level of the broken line portion of the d31 to d0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, and vblast signals indicates undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. vbclk (input) a25 to a0 (output) csz7 to csz0 (output) wrz3 to wrz0 (output) d31 to d0 (output) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) dc3 to dc0 (output) t1 tw1 tw2 t2 ta t1 t2 <2> <2> <8> <10> <9> <8> <8> <8> <10> <9> <10> <9> <1> <17> <3> <3> <17> <17> <17> <11> <12> <16> <18> <19> <19> invalid chapter 10 nb85e500 212 design manual a13195ej5v0dm (3) sram read/write timing (1/2) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time from vbclk to address <2> t ad t dka + 0.4 note t dka + 2.5 note ns delay time from vbclk to csz <3> t cszd1 t dkc + 0.5 note t dkc + 2.5 note ns delay time from vbclk to rdz <4> t rdzd1 1.5 5.4 ns delay time from vbclk to rdz <5> t rdzd2 1.5 5.0 ns data setup time (to vbclk )<6>t ds1 0ns data hold time (from vbclk )<7>t dh1 1.0 ns delay time from vbclk to bcystz <8> t bcyd 1.6 t dks1 + 1.7 note ns waitz setup time (to vbclk )<9>t wts 0ns waitz hold time (from vbclk ) <10> t wth 0.9 ns delay time from vbclk to vbwait, vbahld, vblast <11> t vrd1 5.6 ns delay time from vbclk to vbwait, vbahld, vblast <12> t vrd2 1.2 ns delay time from vbclk to vbd <13> t vbd1 6.5 ns delay time from vbclk to vbd <14> t vbd2 1.7 ns delay time from vbclk to dc <15> t dcd1 t dks1 + 0.7 note t dks1 + 3.1 note ns delay time from vbclk to dc <16> t dcd2 1.8 6.0 ns delay time from vbclk to wrz <17> t wrzd 1.6 4.9 ns delay time from vbclk to data <18> t dd1 t dkd1 + 0.4 note t dkd1 + 2.0 note ns delay time from vbclk to data <19> t dd2 t dkd0 + 0.4 note t dkd0 + 2.0 note ns note t dka : delay time from vbclk to vba t dkc : delay time from vbclk to vdcsz, vdselpz t dks1 : delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp t dkd1 : delay time from vbclk to vbd data t dkd0 : delay time from vbclk to vbd data the above are the electrical specifications of the nb85e (or nb85et). refer to section 7. 4. 4 ac characteristics (or 9. 4. 4 ac characteristics ). chapter 10 nb85e500 213 design manual a13195ej5v0dm (3) sram read/write timing (2/2) remarks 1. t1, t2: basic state in which nb85e500 access is performed 2. the level of the broken line portion of the d31 to d0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, vblast, and vbd31 to vbd0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. vbclk (input) a25 to a0 (output) t1 t2 csz7 to csz0 (output) rdz (output) d31 to d0 (input/output) wrz3 to wrz0 (output) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) vbd31 to vbd0 (input/output) dc3 to dc0 (output) t1 t2 t1 t2 t1 <2> <2> <4> <5> <4> <6> <8> <11> <12> <8> <8> <8> <10> <9> <13> <14> <7> read cycle read cycle write cycle write cycle <10> <9> hi-z hi-z <1> <3> <3> <17> <17> <17> <17> <16> <15> <15> <19> <19> <18> <19> invalid chapter 10 nb85e500 214 design manual a13195ej5v0dm (4) sdram write timing parameter symbol conditions min. max. unit delay time from vbclk to data <19> t dd2 t dkd0 + 0.4 note t dkd0 + 2.0 note ns note t dkd0 : delay time from vbclk to vbd data the above is the electrical specifications of the nb85e (or nb85et). refer to section 7. 4. 4 ac characteristics (or 9. 4. 4 ac characteristics ). note signal of the nu85e502 remarks 1. tw: wait state tact: bank active command state twr: write command state twpre: state indicating a precharge twe: state indicating the end of a write cycle 2. the level of the broken line portion of the vbd31 to vbd0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. the level of the broken line portion of the d31 to d0 signals is undefined. a25 to a0 (output) sdcasz (output) tact twr sdrasz (output) sdwez (output) twpre vbclk (input) twe tw d31 to d0 (output) <19> vbd31 to vbd0 (input) note note note note chapter 10 nb85e500 215 design manual a13195ej5v0dm (5) sdram sequential write timing parameter symbol conditions min. max. unit delay time from vbclk to data <18> t dd1 t dkd1 + 0.4 note t dkd1 + 2.0 note ns delay time from vbclk to data <19> t dd2 t dkd0 + 0.4 note t dkd0 + 2.0 note ns note t dkd1 : delay time from vbclk to vbd data t dkd0 : delay time from vbclk to vbd data the above are the electrical specifications of the nb85e (or nb85et). refer to section 7. 4. 4 ac characteristics (or 9. 4. 4 ac characteristics ). note signal of the nu85e502 remarks 1. tw: wait state tprec: bank precharge command state tbcw: wait state inserted by setting the bcw1 and bcw0 bits of the sdram configuration register n (scrn) (n = 0 to 7) tact: bank active command state twr: write command state twpre:state indicating a precharge twe: state indicating the end of a write cycle 2. the level of the broken line portion of the vbd31 to vbd0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. the level of the broken line portion of the d31 to d0 signals is undefined. a25 to a0 (output) tprec tbcw tact tbcw twr twr sdrasz (output) twpre vbclk (input) twe tw d31 to d0 (output) <18> <19> vbd31 to vbd0 (input) sdcasz (output) sdwez (output) note note note chapter 10 nb85e500 216 design manual a13195ej5v0dm (6) sdram refresh timing parameter symbol conditions min. max. unit delay time from vbclk to refrqz ? t rfrqd 1.5 4.9 ns selfref setup time (to vbclk ) ? t srfs 0.8 ns selfref hold time (from vbclk ) ? t srfh 1.0 ns delay time from ct502in1 to csz ? t cszd2 t c2i1d + 0.4 note t c2i1d + 2.3 note ns note t c2i1d : delay time from vbclk to ct502i1 the above is the electrical specifications of the nu85e502. refer to section 12. 4. 4 (3) nu85e500/nb85e500 connection signal timing . remark n = 7 to 0 (7) sdclk output timing parameter symbol conditions min. max. unit delay time from vbclk to sdclk <23> t sdckd 1.1 3.7 ns vbclk (input) sdclk (output) <23> chapter 10 nb85e500 217 design manual a13195ej5v0dm (8) bus hold timing parameter symbol conditions min. max. unit hldrqz setup time (to vbclk ) <24> t hrqs 0ns hldrqz hold time (from vbclk ) <25> t hrqh 0.6 ns delay time from vbclk to hldakz <26> t hakd 1.5 4.6 ns delay time from vbclk to vareq <27> t vaqd 1.6 4.6 ns vaack setup time (to vbclk ) <28> t vaks 0.5 ns vaack hold time (from vbclk ) <29> t vakh 0.8 ns delay time from vaack to vblock <30> t vlkd 1.7 5.6 ns delay time from vaack to vbttyp <31> t vttpd 1.8 6.0 ns delay time from vaack to vbwrite, vbbenz, vdselpz, vdcsz, vbstz, vbbstr <32> t vsbd 1.7 6.1 ns remark the level of the broken line portion of the vblock, vbttyp1, and vbttyp0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. a25 to a0 (output) hldakz (output) hldrqz (input) vblock (output) vbclk (input) vaack (input) vareq (output) vbttyp1, vbttyp0 (output) vbwrite, vbbenz3 to vbbenz0, vdselpz, vdcsz7 to vdcsz0, vbstz, vbbstr (output) <27> <27> <24> <26> <26> <25> bus hold state <28> <29> <30> <31> <30> <32> <31> <32> chapter 10 nb85e500 218 design manual a13195ej5v0dm (9) stop mode timing parameter symbol conditions min. max. unit stprq setup time (to vbclk ) <33> t spqs 0ns stprq hold time (from vbclk ) <34> t spqh 0.7 ns delay time from vbclk to stpak <35> t spakd 1.5 4.7 ns (10) i/o control signal timing parameter symbol conditions min. max. unit delay time from vbclk to iordz <36> t iord during dma flyby transfer 1.6 5.1 ns delay time from vbclk to iowrz <37> t iowd during dma flyby transfer 1.6 5.1 ns vbclk (input) stpak (output) <33> stprq (input) <35> <34> <35> vbclk (input) iordz (output) <36> <36> iowrz (output) <37> <37> chapter 10 nb85e500 219 design manual a13195ej5v0dm (11) nu85e502 connection signal timing parameter symbol conditions min. max. unit ctcsin3 setup time (to vbclk ) <38> t csi3s 0.5 ns ctcsin3 hold time (from vbclk ) <39> t csi3h 0.6 ns ctcsin2 setup time (to vbclk ) <40> t csi2s 0.9 ns ctcsin2 hold time (from vbclk ) <41> t csi2h 0.5 ns ctcsin1 setup time (to vbclk ) <42> t csi1s 0ns ctcsin1 hold time (from vbclk ) <43> t csi1h 0.9 ns delay time from vbclk to ctcson2 <44> t cso2d 1.5 5.0 ns ct502in0 setup time (to vbclk ) <45> t c2i0s 0ns ct502in0 hold time (from vbclk ) <46> t c2i0h 0.5 ns delay time from vbclk to ctlo1 <47> t ctl1d 1.6 5.2 ns remark n = 7 to 0 remark n = 7 to 0 vbclk (input) <38> ctcsin3 (input) <39> <40> ctcsin2 (input) <41> <42> ctcsin1 (input) <43> ctcson2 (output) <44> <44> <45> ct502in0 (input) <46> ctlo1 (output) <47> <47> chapter 10 nb85e500 220 design manual a13195ej5v0dm (12) vsb timing parameter symbol conditions min. max. unit vba setup time (to vbclk ) ? t vbas1 when using page rom 0 ns vba hold time (from vbclk ) ? t vbah1 when using page rom 1.0 ns vdcsz setup time (to vbclk ) ? t cszs1 2.0 ns vdcsz hold time (from vbclk ) ? t cszh1 0.6 ns vbwrite setup time (to vbclk ) ? t vbwrs1 0ns vbwrite hold time (from vbclk ) ? t vbwrh1 1.3 ns vbbenz setup time (to vbclk ) ? t benzs1 0ns vbbenz hold time (from vbclk ) ? t benzh1 1.3 ns vbctyp setup time (to vbclk ) ? t ctyps1 0.8 ns vbctyp hold time (from vbclk ) ? t ctyph1 0.7 ns vbseq setup time (to vbclk ) ? t seqs1 0.9 ns vbseq hold time (from vbclk ) ? t seqh1 1.1 ns vbstz setup time (to vbclk ) ? t stzs1 0ns vbstz hold time (from vbclk ) ? t stzh1 1.2 ns 221 design manual a13195ej5v0dm [memo] chapter 10 nb85e500 222 design manual a13195ej5v0dm (13) npb timing (1/2) parameter symbol conditions min. max. unit vpa address setup time (to vpstb ) <48> t vpas 20 ns vpa address hold time (from vpstb ) <49> t vpah 20 ns vpwrite setup time (to vpstb ) <50> t vpwrs 20 ns vpwrite hold time (from vpstb ) <51> t vpwrh 20 ns vpd data setup time (to vpstb ) <52> t vpds 20 ns vpd data hold time (from vpstb ) <53> t vpdh 20 ns delay time from vpstb to vpd data <54> t vpdd 1.1 9.5 ns vpubenz setup time (to vpstb ) <55> t vpubs 20 ns vpubenz hold time (from vpstb ) <56> t vpubh 20 ns delay time from vpstb to ctcson4 <57> t cso4d 5ns delay time from vpstb to ctcson3 <58> t cso3d 5ns delay time from vpstb to ctcson1 <59> t cso1d 5ns delay time from vpstb to ctcson0 <60> t cso0d 5ns delay time from vpa address to ct502on1 <61> t c2o1d 5ns delay time from vpa address to ct502on0 <62> t c2o0d 5ns remark n = 7 to 0 chapter 10 nb85e500 223 design manual a13195ej5v0dm (13) npb timing (2/2) remark n = 7 to 0 vpa13 to vpa0 (input) vpd15 to vpd0 (input) vpstb (input) ctcson4 (output) <57> ctcson3 (output) <58> ctcson1 (output) <59> ctcson0 (output) <60> <61> ct502on1 (output) <62> ct502on0 (output) vpwrite (input) vpd15 to vpd0 (output) vpubenz (input) <48> <49> undefined undefined <50> <51> <52> <53> <54> <55> <56> 224 design manual a13195ej5v0dm chapter 11 nu85e500 (under development) the nu85e500 is used as follows according to the type of external memory that is connected. target cpu core types of connected external memory memory controller (memc) sram, rom, page rom, flash memory nu85e500 nb85e sdram nu85e500 + nu85e502 remark for details of the nu85e502, refer to chapter 12 nu85e502 . 11. 1 outline the nu85e500 is a basic core macro used to control external memory. it features on chip sram, and i/o controller, and a page rom controller. the nu85e500 can be used to start the external bus cycle when it is connected to the nb85e via vsb. it can also be used to control sdram by connecting an sdram controller (nu85e502) to the nu85e500. 11. 1. 1 symbol diagram number of grids 35.6k grids 106.0k grids (including wiring area) number of separation simulation patterns 14.3k chapter 11 nu85e500 225 design manual a13195ej5v0dm vptclk in phtest in out phtdo (1:0) csz (7:0) astbz dstbz mpxcz rdcyz busst benz (3:0) refrqz selfref bcystz sdclk stprq stpak mce mpxen bcpen a (25:0) rdz wrz (3:0) iordz iowrz waitz hldrqz hldakz dc (3:0) di (31:0) vbttyp (1:0) vbd (31:0) vpresz vbahld vblast vbseq (2:0) vbwrite vbstz vareq vpstb vpubenz vpwrite vaack vblock vdselpz vpd (15:0) vbwait vbbstr vpa (13:0) vba (25:0) vbbenz (3:0) vbctyp (2:0) vdcsz (7:0) vbclk out out out out out out out out in out out in out in in in out in out out out out in in out out in in in in out out out out out out out in out in/out in/out in in/out in in/out in in/out in in/out in out out in in in in in in in in out out out out out out out out out out out out in in in in in in out out out out out out out in in in out in in in in in in out out out out out out in out out phtdin (1:0) in ct502i5 (1:0) ctcso0 (4:0) ctlo (1:0) ctcsi7 (3:0) ctcsi6 (3:0) ctcsi5 (3:0) ctcsi4 (3:0) ctcsi3 (3:0) ctcsi2 (3:0) ctcsi1 (3:0) ctcsi0 (3:0) ctcso7 (4:0) ctcso6 (4:0) ctcso5 (4:0) ctcso4 (4:0) ctcso3 (4:0) ctcso2 (4:0) ctcso1 (4:0) ct501o0 (3:0) ct501o1 (3:0) ct501o7 (3:0) ct501i0 (2:0) ct501i3 (2:0) ct501i4 (2:0) ct501i6 (2:0) ct501i7 (2:0) mten ct501i5 (2:0) ct501i2 (2:0) ct501i1 (2:0) ct501o6 (3:0) ct501o5 (3:0) ct501o4 (3:0) ct501o3 (3:0) ct501o2 (3:0) ct502i0 (1:0) ct502o7 (1:0) bcp pisl ctl501 ct502i6 (1:0) ct502i4 (1:0) ct502i3 (1:0) ct502i2 (1:0) ct502i1 (1:0) rwc (7:0) ct502i7 (1:0) ct502o6 (1:0) ct502o5 (1:0) ct502o4 (1:0) ct502o3 (1:0) ct502o2 (1:0) ct502o1 (1:0) ct502o0 (1:0) do (31:0) out chapter 11 nu85e500 226 design manual a13195ej5v0dm 11. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins (1/3) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) vbclk 0.135 2.035 vaack 0.157 2.057 vba25 0.051 1.951 vpstb 0.017 1.917 vba24 0.120 2.020 vpubenz 0.036 1.936 vba23 0.140 2.040 vpa13 0.013 1.913 vba22 0.166 2.066 vpa12 0.016 1.916 vba21 0.133 2.033 vpa11 0.014 1.914 vba20 0.101 2.001 vpa10 0.016 1.916 vba19 0.166 2.066 vpa9 0.013 1.913 vba18 0.014 1.914 vpa8 0.020 1.920 vba17 0.106 2.006 vpa7 0.015 1.915 vba16 0.494 2.394 vpa6 0.037 1.937 vba15 0.097 1.997 vpa5 0.015 1.915 vba14 0.091 1.991 vpa4 0.014 1.914 vba13 0.108 2.008 vpa3 0.013 1.913 vba12 0.110 2.010 vpa2 0.021 1.921 vba11 0.056 1.956 vpa1 0.013 1.913 vba10 0.129 2.029 vpa0 0.016 1.916 vba9 0.100 2.000 vpwrite 0.012 1.912 vba8 0.163 2.063 stprq 0.161 2.061 vba7 0.143 2.043 mce 0.110 2.010 vba6 0.021 1.921 bcpen 0.113 2.013 vba5 0.189 2.089 di31 0.027 1.927 vba4 0.054 1.954 di30 0.018 1.918 vba3 0.119 2.019 di29 0.025 1.925 vba2 0.025 1.925 di28 0.019 1.919 vba1 0.131 2.031 di27 0.018 1.918 vba0 0.161 2.061 di26 0.024 1.924 vbctyp2 0.017 1.917 di25 0.018 1.918 vbctyp1 0.022 1.922 di24 0.022 1.922 vbctyp0 0.018 1.918 di23 0.022 1.922 vpresz 0.013 1.913 di22 0.026 1.926 vbseq2 0.016 1.916 di21 0.032 1.932 vbseq1 0.023 1.923 di20 0.024 1.924 vbseq0 0.022 1.922 di19 0.029 1.929 chapter 11 nu85e500 227 design manual a13195ej5v0dm (1) input pins (2/3) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) di18 0.020 1.920 ctcsi32 0.026 1.926 di17 0.016 1.916 ctcsi31 0.039 1.939 di16 0.014 1.914 ctcsi30 0.237 2.137 di15 0.026 1.926 ctcsi23 0.063 1.963 di14 0.024 1.924 ctcsi22 0.126 2.026 di13 0.040 1.940 ctcsi21 0.287 2.187 di12 0.034 1.934 ctcsi20 0.212 2.112 di11 0.018 1.918 ctcsi13 0.143 2.043 di10 0.023 1.923 ctcsi12 0.031 1.931 di9 0.055 1.955 ctcsi11 0.037 1.937 di8 0.030 1.930 ctcsi10 0.196 2.096 di7 0.020 1.920 ctcsi03 0.243 2.143 di6 0.020 1.920 ctcsi02 0.171 2.071 di5 0.024 1.924 ctcsi01 0.165 2.065 di4 0.017 1.917 ctcsi00 0.151 2.051 di3 0.023 1.923 ct502i71 0.017 1.917 di2 0.025 1.925 ct502i70 0.234 2.134 di1 0.028 1.928 ct502i61 0.097 1.997 di0 0.014 1.914 ct502i60 0.094 1.994 waitz 0.063 1.963 ct502i51 0.029 1.929 hldrqz 0.051 1.951 ct502i50 0.201 2.101 selfref 0.184 2.084 ct502i41 0.055 1.955 ctcsi73 0.491 2.391 ct502i40 0.070 1.970 ctcsi72 0.167 2.067 ct502i31 0.227 2.127 ctcsi71 0.130 2.030 ct502i30 0.098 1.998 ctcsi70 0.151 2.051 ct502i21 0.020 1.920 ctcsi63 0.068 1.968 ct502i20 0.181 2.081 ctcsi62 0.018 1.918 ct502i11 0.022 1.922 ctcsi61 0.018 1.918 ct502i10 0.118 2.018 ctcsi60 0.157 2.057 ct502i01 0.015 1.915 ctcsi53 0.198 2.098 ct502i00 0.211 2.111 ctcsi52 0.023 1.923 phtest 0.076 1.976 ctcsi51 0.102 2.002 phtdin1 0.034 1.934 ctcsi50 0.124 2.024 phtdin0 0.054 1.954 ctcsi43 0.089 1.989 vptclk 0.064 1.964 ctcsi42 0.076 1.976 mpxen 0.117 2.017 ctcsi41 0.017 1.917 ct501i72 0.066 1.966 ctcsi40 0.267 2.167 ct501i71 0.096 1.996 ctcsi33 0.069 1.969 ct501i70 0.293 2.193 chapter 11 nu85e500 228 design manual a13195ej5v0dm (1) input pins (3/3) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) ct501i62 0.044 1.944 ct501i30 0.273 2.173 ct501i61 0.044 1.944 ct501i22 0.318 2.218 ct501i60 0.042 1.942 ct501i21 0.094 1.994 ct501i52 0.360 2.260 ct501i20 0.043 1.943 ct501i51 0.121 2.021 ct501i12 0.066 1.966 ct501i50 0.064 1.964 ct501i11 0.123 2.023 ct501i42 0.358 2.258 ct501i10 0.078 1.978 ct501i41 0.077 1.977 ct501i02 0.262 2.162 ct501i40 0.016 1.916 ct501i01 0.193 2.093 ct501i32 0.055 1.955 ct501i00 0.331 2.231 ct501i31 0.062 1.962 (2) output pins (1/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vareq 12.885 ?? a11 13.065 ?? vblock 6.549 0.084 1.984 a10 13.065 ?? vbttyp1 6.581 0.048 1.948 a9 13.068 ?? vbttyp0 6.581 0.048 1.948 a8 13.064 ?? vbbstr 6.575 0.053 1.953 a7 13.066 ?? vdselpz 6.579 0.050 1.950 a6 13.305 ?? vbwait 6.577 0.051 1.951 a5 13.041 ?? vbahld 6.574 0.054 1.954 a4 13.320 ?? vblast 6.571 0.057 1.957 a3 13.067 ?? stpak 12.914 ?? a2 13.071 ?? a25 13.066 ?? a1 13.071 ?? a24 13.054 ?? a0 13.058 ?? a23 13.064 ?? do31 13.071 ?? a22 13.063 ?? do30 13.066 ?? a21 13.069 ?? do29 13.071 ?? a20 13.071 ?? do28 13.067 ?? a19 13.071 ?? do27 13.068 ?? a18 13.063 ?? do26 13.069 ?? a17 13.060 ?? do25 13.069 ?? a16 13.044 ?? do24 13.071 ?? a15 13.069 ?? do23 13.061 ?? a14 13.037 ?? do22 13.063 ?? a13 13.071 ?? do21 13.070 ?? a12 13.045 ?? do20 13.062 ?? chapter 11 nu85e500 229 design manual a13195ej5v0dm (2) output pins (2/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) do19 13.070 ?? csz0 13.054 ?? do18 13.064 ?? benz3 12.962 ?? do17 13.071 ?? benz2 12.968 ?? do16 13.059 ?? benz1 13.307 ?? do15 13.071 ?? benz0 13.328 ?? do14 13.062 ?? bcystz 13.203 ?? do13 13.071 ?? refrqz 13.054 ?? do12 13.070 ?? sdclk 13.071 ?? do11 13.071 ?? ctcso74 13.335 ?? do10 13.070 ?? ctcso73 13.332 ?? do9 13.071 ?? ctcso72 13.118 ?? do8 13.070 ?? ctcso71 13.338 ?? do7 13.071 ?? ctcso70 13.335 ?? do6 13.068 ?? ctcso64 13.338 ?? do5 13.062 ?? ctcso63 13.334 ?? do4 13.071 ?? ctcso62 13.039 ?? do3 13.068 ?? ctcso61 13.274 ?? do2 13.062 ?? ctcso60 13.335 ?? do1 7.907 ?? ctcso54 13.329 ?? do0 7.904 ?? ctcso53 13.337 ?? rdz 12.905 ?? ctcso52 13.202 ?? wrz3 13.175 ?? ctcso51 13.332 ?? wrz2 13.177 ?? ctcso50 13.334 ?? wrz1 13.141 ?? ctcso44 13.325 ?? wrz0 13.187 ?? ctcso43 13.291 ?? iordz 13.014 ?? ctcso42 13.041 ?? iowrz 12.873 ?? ctcso41 13.267 ?? hldakz 13.338 ?? ctcso40 13.336 ?? dc3 13.320 ?? ctcso34 13.311 ?? dc2 13.035 ?? ctcso33 13.311 ?? dc1 13.048 ?? ctcso32 13.279 ?? dc0 13.071 ?? ctcso31 13.331 ?? csz7 13.037 ?? ctcso30 13.309 ?? csz6 13.311 ?? ctcso24 13.336 ?? csz5 13.035 ?? ctcso23 13.311 ?? csz4 12.999 ?? ctcso22 12.939 ?? csz3 13.002 ?? ctcso21 13.331 ?? csz2 13.071 ?? ctcso20 13.330 ?? csz1 13.025 ?? ctcso14 13.277 ?? chapter 11 nu85e500 230 design manual a13195ej5v0dm (2) output pins (3/3) pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) ctcso13 13.251 ?? ct501o63 13.334 ?? ctcso12 13.039 ?? ct501o62 13.256 ?? ctcso11 13.324 ?? ct501o61 13.334 ?? ctcso10 13.323 ?? ct501o60 13.323 ?? ctcso04 13.278 ?? ct501o53 13.336 ?? ctcso03 13.255 ?? ct501o52 13.031 ?? ctcso02 12.931 ?? ct501o51 13.338 ?? ctcso01 13.326 ?? ct501o50 13.108 ?? ctcso00 13.324 ?? ct501o43 13.283 ?? ctlo1 13.210 ?? ct501o42 13.248 ?? ctlo0 13.261 ?? ct501o41 13.283 ?? mten 13.314 ?? ct501o40 13.338 ?? ct502o71 13.224 ?? ct501o33 13.325 ?? ct502o70 13.328 ?? ct501o32 13.333 ?? ct502o61 13.335 ?? ct501o31 13.338 ?? ct502o60 13.338 ?? ct501o30 13.333 ?? ct502o51 13.140 ?? ct501o23 13.334 ?? ct502o50 13.219 ?? ct501o22 13.322 ?? ct502o41 13.334 ?? ct501o21 13.338 ?? ct502o40 13.330 ?? ct501o20 13.328 ?? ct502o31 13.332 ?? ct501o13 13.170 ?? ct502o30 13.324 ?? ct501o12 13.324 ?? ct502o21 13.130 ?? ct501o11 13.319 ?? ct502o20 13.338 ?? ct501o10 13.318 ?? ct502o11 13.332 ?? ct501o03 13.324 ?? ct502o10 13.335 ?? ct501o02 13.228 ?? ct502o01 13.320 ?? ct501o01 13.107 ?? ct502o00 13.325 ?? ct501o00 13.313 ?? phtdo1 13.223 ?? bcp 13.286 ?? phtdo0 13.309 ?? pisl 13.338 ?? astbz 13.172 ?? ctl501 13.308 ?? dstbz 13.161 ?? rwc7 13.296 ?? mpxcz 12.961 ?? rwc6 13.334 ?? rdcyz 13.039 ?? rwc5 13.323 ?? busst 12.955 ?? rwc4 13.282 ?? ct501o73 13.331 ?? rwc3 13.315 ?? ct501o72 12.986 ?? rwc2 13.242 ?? ct501o71 13.148 ?? rwc1 13.303 ?? ct501o70 13.063 ?? rwc0 13.325 ?? chapter 11 nu85e500 231 design manual a13195ej5v0dm (3) i/o pins pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vdcsz7 6.446 0.183 2.083 vbd12 6.338 0.290 2.190 vdcsz6 6.374 0.254 2.154 vbd11 6.345 0.284 2.184 vdcsz5 6.320 0.308 2.208 vbd10 6.344 0.285 2.185 vdcsz4 6.298 0.331 2.231 vbd9 6.329 0.299 2.199 vdcsz3 6.211 0.418 2.318 vbd8 6.315 0.314 2.214 vdcsz2 6.355 0.273 2.173 vbd7 6.329 0.300 2.200 vdcsz1 6.313 0.316 2.216 vbd6 6.344 0.285 2.185 vdcsz0 6.477 0.152 2.052 vbd5 6.314 0.315 2.215 vbbenz3 6.428 0.200 2.100 vbd4 6.318 0.311 2.211 vbbenz2 6.462 0.166 2.066 vbd3 6.359 0.270 2.170 vbbenz1 6.489 0.140 2.040 vbd2 6.333 0.296 2.196 vbbenz0 6.484 0.145 2.045 vbd1 6.366 0.263 2.163 vbd31 6.385 0.244 2.144 vbd0 6.394 0.235 2.135 vbd30 6.375 0.254 2.154 vbwrite 6.492 0.137 2.037 vbd29 6.383 0.246 2.146 vbstz 6.394 0.234 2.134 vbd28 6.366 0.263 2.163 vpd15 6.493 0.188 2.088 vbd27 6.364 0.265 2.165 vpd14 6.555 0.120 2.020 vbd26 6.393 0.236 2.136 vpd13 6.525 0.150 2.050 vbd25 6.390 0.239 2.139 vpd12 6.530 0.145 2.045 vbd24 6.399 0.230 2.130 vpd11 6.504 0.176 2.076 vbd23 6.373 0.256 2.156 vpd10 6.519 0.161 2.061 vbd22 6.394 0.235 2.135 vpd9 6.519 0.161 2.061 vbd21 6.378 0.251 2.151 vpd8 6.537 0.143 2.043 vbd20 6.373 0.256 2.156 vpd7 6.503 0.218 2.118 vbd19 6.373 0.256 2.156 vpd6 6.514 0.207 2.107 vbd18 6.384 0.244 2.144 vpd5 6.508 0.213 2.113 vbd17 6.346 0.282 2.182 vpd4 6.534 0.188 2.088 vbd16 6.366 0.262 2.162 vpd3 6.475 0.246 2.146 vbd15 6.364 0.264 2.164 vpd2 6.478 0.244 2.144 vbd14 6.362 0.266 2.166 vpd1 6.493 0.228 2.128 vbd13 6.348 0.281 2.181 vpd0 6.489 0.233 2.133 11. 2 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in the test program. failure to this so will result in the propagation of undefined values. chapter 11 nu85e500 232 design manual a13195ej5v0dm 11. 3 pin functions (1/3) pin name i/o function vbclk input internal system clock input vdcsz7 to vdcsz0 i/o chip select i/o vba25 to vba0 input address input vbbenz3 to vbbenz0 i/o byte enable i/o vbctyp2 to vbctyp0 input bus cycle status input vbd31 to vbd0 i/o data i/o vpresz input reset input vbseq2 to vbseq0 input sequential status input vbwrite i/o read/write status i/o vbstz i/o transfer start i/o vareq output bus access right request output vaack input bus access right acknowledge input vblock output bus lock output vbttyp1, vbttyp0 output bus transfer type output vbbstr output burst read status output vdselpz output peripheral i/o area access status output vbwait output wait response output vbahld output address hold response output vblast output last response output vpstb input data strobe input (for npb) vpubenz input upper byte enable input (for npb) vpa13 to vpa0 input address input (for npb) vpwrite input write access strobe input (for npb) vpd15 to vpd0 i/o data i/o (for npb) stprq input stop mode request input nb85e connection pins stpak output acknowledge output for stprq input mce input men bit reset value control input for bct register (n = 7 to 0) initial setting pins bcpen input bcp bit reset value control input for bcp register a25 to a0 output external memory address output di31 to di0 input external memory data input do31 to do0 output external memory data output rdz output sram/page rom read strobe output wrz3 to wrz0 output sram/page rom write strobe output iordz output external i/o read strobe output iowrz output external i/o write strobe output external memory connection pins waitz input wait request input chapter 11 nu85e500 233 design manual a13195ej5v0dm (2/3) pin name i/o function hldrqz input external bus hold request input hldakz output external bus hold request acknowledge output dc3 to dc0 output data bus control output csz7 to csz0 output chip select output benz3 to benz0 output byte enable output bcystz output bus cycle start status output refrqz output refresh status output selfref input self refresh request input external memory connection pins sdclk output sdram sync clock output ctcsi73 to ctcsi70 input control input from nu85e502 (for cs7 area) ctcsi63 to ctcsi60 input control input from nu85e502 (for cs6 area) ctcsi53 to ctcsi50 input control input from nu85e502 (for cs5 area) ctcsi43 to ctcsi40 input control input from nu85e502 (for cs4 area) ctcsi33 to ctcsi30 input control input from nu85e502 (for cs3 area) ctcsi23 to ctcsi20 input control input from nu85e502 (for cs2 area) ctcsi13 to ctcsi10 input control input from nu85e502 (for cs1 area) ctcsi03 to ctcsi00 input control input from nu85e502 (for cs0 area) ctcso74 to ctcso70 output control output to nu85e502 (for cs7 area) ctcso64 to ctcso60 output control output to nu85e502 (for cs6 area) ctcso54 to ctcso50 output control output to nu85e502 (for cs5 area) ctcso44 to ctcso40 output control output to nu85e502 (for cs4 area) ctcso34 to ctcso30 output control output to nu85e502 (for cs3 area) ctcso24 to ctso20 output control output to nu85e502 (for cs2 area) ctcso14 to ctcso10 output control output to nu85e502 (for cs1 area) ctcso04 to ctcso00 output control output to nu85e502 (for cs0 area) ctlo1, ctlo0 output control output to nu85e502 mten output test mode enable output to nu85e502 ct502i71, ct502i70 input control input from nu85e502 (for cs7 area) ct502i61, ct502i60 input control input from nu85e502 (for cs6 area) ct502i51, ct502i50 input control input from nu85e502 (for cs5 area) ct502i41, ct502i40 input control input from nu85e502 (for cs4 area) ct502i31, ct502i30 input control input from nu85e502 (for cs3 area) ct502i21, ct502i20 input control input from nu85e502 (for cs2 area) ct502i11, ct502i10 input control input from nu85e502 (for cs1 area) nu85e502 connection pins ct502i01, ct502i00 input control input from nu85e502 (for cs0 area) chapter 11 nu85e500 234 design manual a13195ej5v0dm (3/3) pin name i/o function ct502o71, ct502o70 output control output to nu85e502 (for cs7 area) ct502o61, ct502o60 output control output to nu85e502 (for cs6 area) ct502o51, ct502o50 output control output to nu85e502 (for cs5 area) ct502o41, ct502o40 output control output to nu85e502 (for cs4 area) ct502o31, ct502o30 output control output to nu85e502 (for cs3 area) ct502o21, ct502o20 output control output to nu85e502 (for cs2 area) ct502o11, ct502o10 output control output to nu85e502 (for cs1 area) nu85e502 connection pins ct502o01, ct502o00 output control output to nu85e502 (for cs0 area) phtest input peripheral test mode status input phtdin1, phtdin0 input peripheral macro test input phtdo1, phtdo0 output peripheral macro test output test mode pins vptclk input test clock input mpxen input nec reserved pin (input a low level) astbz output nec reserved pin (leave open) dstbz output nec reserved pin (leave open) mpxcz output nec reserved pin (leave open) rdcyz output nec reserved pin (leave open) busst output nec reserved pin (leave open) ct501i72 to ct501i70 input nec reserved pin (input a low level) ct501i62 to ct501i60 input nec reserved pin (input a low level) ct501i52 to ct501i50 input nec reserved pin (input a low level) ct501i42 to ct501i40 input nec reserved pin (input a low level) ct501i32 to ct501i30 input nec reserved pin (input a low level) ct501i22 to ct501i20 input nec reserved pin (input a low level) ct501i12 to ct501i10 input nec reserved pin (input a low level) ct501i02 to ct501i00 input nec reserved pin (input a low level) ct501o73 to ct501o70 output nec reserved pin (leave open) ct501o63 to ct501o60 output nec reserved pin (leave open) ct501o53 to ct501o50 output nec reserved pin (leave open) ct501o43 to ct501o40 output nec reserved pin (leave open) ct501o33 to ct501o30 output nec reserved pin (leave open) ct501o23 to ct501o20 output nec reserved pin (leave open) ct501o13 to ct501o10 output nec reserved pin (leave open) ct501o03 to ct501o00 output nec reserved pin (leave open) bcp output nec reserved pin (leave open) pisl output nec reserved pin (leave open) ctl501 output nec reserved pin (leave open) nec reserved pins rwc7 to rwc0 output nec reserved pin (leave open) chapter 11 nu85e500 235 design manual a13195ej5v0dm 11. 4 electrical specifications (preliminary) the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 11. 4. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 11. 4. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 15.0 ns 11. 4. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode 0.18 0.27 ma/mhz supply current i dd2 in stop mode 0 1.0 a remarks 1. the above supply current value is a reference value calculated from the number of grids. 2. the typ. value is a reference value for when t a = 25 c, v dd = 3.3 v. chapter 11 nu85e500 236 design manual a13195ej5v0dm 11. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) (1) sram/page rom read timing (1/3) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time from vbclk to address <2> t ad t dka + 0.7 note t dka + 3.4 note ns delay time from vbclk to csz <3> t cszd1 t dkc + 0.8 note t dkc + 3.4 note ns delay time from vbclk to rdz <4> t rdzd1 2.1 6.2 ns delay time from vbclk to rdz <5> t rdzd2 1.9 5.3 ns data setup time (to vbclk )<6>t dis 0ns data hold time (from vbclk )<7>t dih 1.5 ns delay time from vbclk to bcystz <8> t bcyd 1.7 t dks1 + 1.8 note ns waitz setup time (to vbclk )<9>t wts 0ns waitz hold time (from vbclk ) <10> t wth 1.3 ns delay time from vbclk to vbwait, vbahld, vblast <11> t vrd1 5.9 ns delay time from vbclk to vbwait, vbahld, vblast <12> t vrd2 1.6 ns delay time from vbclk to vbd <13> t vbd1 6.5 ns delay time from vbclk to vbd <14> t vbd2 1.7 ns delay time from vbclk to dc <15> t dcd1 t dks1 + 0.8 note t dks1 + 2.9 note ns note t dka : delay time from vbclk to vba t dkc : delay time from vbclk to vdcsz, vdselpz t dks1 : delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp the above are the electrical specifications of the nb85e. refer to section 7. 4. 4 ac characteristics . chapter 11 nu85e500 237 design manual a13195ej5v0dm (1) sram/page rom read timing (2/3) (a) when wait is inserted remarks 1. t1, t2: basic state in which nu85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) ti: idle state inserted by setting bus cycle control register (bcc) 2. the level of the broken line portion of the di31 to di0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, vblast, and vbd31 to vbd0 signals indicates the undefined state (weak unknown) in which the bus holder in the nb85e is driving. vbclk (input) a25 to a0 (output) t1 t2 csz7 to csz0 (output) rdz (output) di31 to di0 (input) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) vbd31 to vbd0 (output) dc3 to dc0 (output) t1 tw1 t2 ti <2> <4> <1> <5> <7> <6> <8> <10> <9> <11> <12> <13> <14> <15> <8> <4> <5> <7> <6> <8> <8> <10> <9> <13> <14> <2> <3> <3> chapter 11 nu85e500 238 design manual a13195ej5v0dm (1) sram/page rom read timing (3/3) (b) when address setting wait is inserted remarks 1. t1, t2: basic state in which nu85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) tw2: wait state through waitz pin input ta: address setting wait state inserted by setting the address setting wait control register (asc) 2. the level of the broken line portion of the di31 to di0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, vblast, and vbd31 to vbd0 signals indicates the undefined state (weak unknown) in which the bus holder in the nb85e is driving. vbclk (input) a25 to a0 (output) t1 tw1 csz7 to csz0 (output) rdz (output) di31 to di0 (input) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) vbd31 to vbd0 (output) dc3 to dc0 (output) tw2 t2 ta t1 t2 <2> <1> <2> <4> <5> <4> <7> <6> <8> <10> <9> <11> <12> <15> <8> <8> <8> <10> <9> <13> <14> <10> <9> <3> <3> chapter 11 nu85e500 239 design manual a13195ej5v0dm (2) sram write timing (1/3) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time from vbclk to address <2> t ad t dka + 0.7 note t dka + 3.4 note ns delay time from vbclk to csz <3> t cszd1 t dkc + 0.8 note t dkc + 3.4 note ns delay time from vbclk to bcystz <8> t bcyd 1.7 t dks1 + 1.8 note ns waitz setup time (to vbclk )<9>t wts 0ns waitz hold time (from vbclk ) <10> t wth 1.3 ns delay time from vbclk to vbwait, vbahld, vblast <11> t vrd1 5.9 ns delay time from vbclk to vbwait, vbahld, vblast <12> t vrd2 1.6 ns delay time from vbclk to dc <16> t dcd2 1.9 5.9 ns delay time from vbclk to wrz <17> t wrzd 2.0 5.6 ns delay time from vbclk to data <18> t dod1 t dkd1 + 0.3 note t dkd1 + 1.7 note ns delay time from vbclk to data <19> t dod2 t dkd0 + 0.3 note t dkd0 + 1.7 note ns delay time from vbbenz to benz ? t bnzd 0.5 2.2 ns note t dka : delay time from vbclk to vba t dkc : delay time from vbclk to vdcsz, vdselpz t dks1 : delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp t dkd1 : delay time from vbclk to vbd data t dkd0 : delay time from vbclk to vbd data the above are the electrical specifications of the nb85e. refer to section 7. 4. 4 ac characteristics . chapter 11 nu85e500 240 design manual a13195ej5v0dm (2) sram write timing (2/3) (a) when wait is inserted remarks 1. t1, t2: basic state in which nu85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) ti: idle state inserted by setting bus cycle control register (bcc) 2. the level of the broken line portion of the do31 to do0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, and vblast signals indicates undefined state (weak unknown) in which the bus holder in the nb85e is driving. vbclk (input) a25 to a0 (output) csz7 to csz0 (output) wrz3 to wrz0 (output) do31 to do0 (output) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) dc3 to dc0 (output) t1 t2 t1 tw1 t2 ti <2> <1> <2> <17> <17> <17> <17> <19> <8> <8> <8> <8> <9> <10> <9> <10> <11> <12> <16> <3> <3> <18> chapter 11 nu85e500 241 design manual a13195ej5v0dm (2) sram write timing (3/3) (b) when address setting wait is inserted remarks 1. t1, t2: basic state in which nu85e500 access is performed tw1: wait state inserted by setting data wait control registers 0, 1 (dwc0, dwc1) tw2: wait state through waitz pin input ta: address setting wait state inserted by setting the address setting wait control register (asc) 2. the level of the broken line portion of the do31 to do0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, and vblast signals indicates undefined state (weak unknown) in which the bus holder in the nb85e is driving. vbclk (input) a25 to a0 (output) csz7 to csz0 (output) wrz3 to wrz0 (output) do31 to do0 (output) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) dc3 to dc0 (output) t1 tw1 tw2 t2 ta t1 t2 <2> <2> <8> <10> <9> <8> <8> <8> <10> <9> <10> <9> <1> <17> <3> <3> <17> <18> <19> <17> <17> <11> <12> <16> chapter 11 nu85e500 242 design manual a13195ej5v0dm (3) sram read/write timing (1/2) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time from vbclk to address <2> t ad t dka + 0.7 note t dka + 3.4 note ns delay time from vbclk to csz <3> t cszd1 t dkc + 0.8 note t dkc + 3.4 note ns delay time from vbclk to rdz <4> t rdzd1 2.1 6.2 ns delay time from vbclk to rdz <5> t rdzd2 1.9 5.3 ns data setup time (to vbclk )<6>t dis 0ns data hold time (from vbclk )<7>t dih 1.5 ns delay time from vbclk to bcystz <8> t bcyd 1.7 t dks1 + 1.8 note ns waitz setup time (to vbclk )<9>t wts 0ns waitz hold time (from vbclk ) <10> t wth 1.3 ns delay time from vbclk to vbwait, vbahld, vblast <11> t vrd1 5.9 ns delay time from vbclk to vbwait, vbahld, vblast <12> t vrd2 1.6 ns delay time from vbclk to vbd <13> t vbd1 6.5 ns delay time from vbclk to vbd <14> t vbd2 1.7 ns delay time from vbclk to dc <15> t dcd1 t dks1 + 0.8 note t dks1 + 2.9 note ns delay time from vbclk to dc <16> t dcd2 1.9 5.9 ns delay time from vbclk to wrz <17> t wrzd 2.0 5.6 ns delay time from vbclk to data <18> t dod1 t dkd1 + 0.3 note t dkd1 + 1.7 note ns delay time from vbclk to data <19> t dod2 t dkd0 + 0.3 note t dkd0 + 1.7 note ns note t dka : delay time from vbclk to vba t dkc : delay time from vbclk to vdcsz, vdselpz t dks1 : delay time from vbclk to vbstz, vbsize, vbwrite, vbctyp t dkd1 : delay time from vbclk to vbd data t dkd0 : delay time from vbclk to vbd data the above are the electrical specifications of the nb85e. refer to section 7. 4. 4 ac characteristics . chapter 11 nu85e500 243 design manual a13195ej5v0dm (3) sram read/write timing (2/2) remarks 1. t1, t2: basic state in which nu85e500 access is performed 2. the level of the broken line portion of the di31 to di0 and do31 to do0 signals is undefined. the level of the broken line portion of the vbwait, vbahld, vblast, and vbd31 to vbd0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e is driving. vbclk (input) a25 to a0 (output) t1 t2 csz7 to csz0 (output) rdz (output) di31 to di0 (input) wrz3 to wrz0 (output) bcystz (output) waitz (input) vbwait (output) vbahld (output) vblast (output) vbd31 to vbd0 (input/output) dc3 to dc0 (output) t1 t2 t1 t2 t1 <2> <2> <4> <5> <4> <6> <8> <11> <12> <8> <8> <8> <10> <9> <13> <14> <7> read cycle read cycle write cycle write cycle <10> <9> <1> <3> <3> do31 to do0 (output) <19> <18> <18> <17> <17> <17> <17> <16> <15> <15> chapter 11 nu85e500 244 design manual a13195ej5v0dm (4) sdram write timing parameter symbol conditions min. max. unit delay time from vbclk to data <19> t dod2 t dkd0 + 0.3 note t dkd0 + 1.7 note ns note t dkd0 : delay time from vbclk to vbd data the above is the electrical specifications of the nb85e. refer to section 7. 4. 4 ac characteristics . note signal of the nu85e502 remarks 1. tw: wait state tprec: bank precharge command state tbcw: wait state inserted by setting the bcw1 and bcw0 bits of the sdram configuration register n (scrn) (n = 7 to 0) tact: bank active command state twr: write command state twpre:state indicating a precharge twe: state indicating the end of a write cycle 2. the level of the broken line portion of the vbd31 to vbd0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e is driving. the level of the broken line portion of the do31 to do0 signals is undefined. a25 to a0 (output) tprec tbcw tact tbcw twr twpre vbclk (input) twe tw do31 to do0 (output) <19> vbd31 to vbd0 (input) sdcasz (output) sdrasz (output) sdwez (output) note note note note chapter 11 nu85e500 245 design manual a13195ej5v0dm (5) sdram sequential write timing parameter symbol conditions min. max. unit delay time from vbclk to data (sdram sequential write) <20> t dod3 1.9 5.7 ns vbd data setup time (to vbclk ) <21> t vbds 0ns vbd data hold time (from vbclk ) <22> t vbdh 1.8 ns note signal of the nu85e502 remarks 1. tw: wait state tprec: bank precharge command state tbcw: wait state inserted by setting the bcw1 and bcw0 bits of the sdram configuration register n (scrn) (n = 0 to 7) tact: bank active command state twr: write command state twpre: state indicating a precharge twe: state indicating the end of a write cycle 2. the level of the broken line portion of the vbd31 to vbd0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e is driving. the level of the broken line portion of the do31 to do0 signals is undefined. a25 to a0 (output) tprec sdcasz (output) tbcw tact tbcw twr twr sdrasz (output) sdwez (output) twpre vbclk (input) twe tw do31 to do0 (output) <20> vbd31 to vbd0 (input) <21> <22> <21> <20> note note note chapter 11 nu85e500 246 design manual a13195ej5v0dm (6) sdram refresh timing parameter symbol conditions min. max. unit delay time from vbclk to refrqz ? t rfrqd 2.0 5.7 ns selfref setup time (to vbclk ) ? t srfs 0ns selfref hold time (from vbclk ) ? t srfh 1.4 ns delay time from ct502in1 to csz ? t cszd2 t c2i1d + 0.5 note t c2i1d + 2.4 note ns note t c2i1d : delay time from vbclk to ct502i1 the above is the electrical specifications of the nu85e502. refer to section 12. 4. 4 (3) nu85e500/nb85e500 connection signal timing . remark n = 7 to 0 (7) sdclk output timing parameter symbol conditions min. max. unit delay time from vbclk to sdclk <23> t sdckd 1.6 4.5 ns vbclk (input) sdclk (output) <23> chapter 11 nu85e500 247 design manual a13195ej5v0dm (8) bus hold timing parameter symbol conditions min. max. unit hldrqz setup time (to vbclk ) <24> t hrqs 0ns hldrqz hold time (from vbclk ) <25> t hrqh 1.2 ns delay time from vbclk to hldakz <26> t hakd 2.0 5.6 ns delay time from vbclk to vareq <27> t vaqd 1.9 5.3 ns vaack setup time (to vbclk ) <28> t vaks 0ns vaack hold time (from vbclk ) <29> t vakh 1.6 ns delay time from vaack to vblock <30> t vlkd 0.6 2.4 ns delay time from vaack to vbttyp <31> t vttpd 0.4 1.9 ns delay time from vaack to vbwrite, vbbenz, vdselpz, vdcsz, vbstz, vbbstr <32> t vsbd 0.5 2.5 ns remark the level of the broken line portion of the vblock, vbttyp1, and vbttyp0 signals indicates undefined state (weak unknown) in which the bus holder in the nb85e is driving. a25 to a0 (output) hldakz (output) hldrqz (input) vblock (output) vbclk (input) vaack (input) vareq (output) vbttyp1, vbttyp0 (output) vbwrite, vbbenz3 to vbbenz0, vdselpz, vdcsz7 to vdcsz0, vbstz, vbbstr (output) <27> <27> <24> <26> <26> <25> bus hold state <28> <29> <30> <31> <30> <32> <31> <32> chapter 11 nu85e500 248 design manual a13195ej5v0dm (9) stop mode timing parameter symbol conditions min. max. unit stprq setup time (to vbclk ) <33> t spqs 0ns stprq hold time (from vbclk ) <34> t spqh 1.2 ns delay time from vbclk to stpak <35> t spakd 1.9 5.2 ns (10) i/o control signal timing parameter symbol conditions min. max. unit delay time from vbclk to iordz <36> t iord during dma flyby transfer 2.1 5.9 ns delay time from vbclk to iowrz <37> t iowd during dma flyby transfer 1.9 5.6 ns vbclk (input) stpak (output) <33> stprq (input) <35> <34> <35> vbclk (input) iordz (output) <36> <36> iowrz (output) <37> <37> chapter 11 nu85e500 249 design manual a13195ej5v0dm (11) nu85e502 connection signal timing parameter symbol conditions min. max. unit ctcsin3 setup time (to vbclk ) <38> t csi3s 0ns ctcsin3 hold time (from vbclk ) <39> t csi3h 0.8 ns ctcsin2 setup time (to vbclk ) <40> t csi2s 0ns ctcsin2 hold time (from vbclk ) <41> t csi2h 1.4 ns ctcsin1 setup time (to vbclk ) <42> t csi1s 0ns ctcsin1 hold time (from vbclk ) <43> t csi1h 1.3 ns delay time from vbclk to ctcson2 <44> t cso2d 1.9 5.7 ns ct502in0 setup time (to vbclk ) <45> t c2i0s 0ns ct502in0 hold time (from vbclk ) <46> t c2i0h 0.5 ns delay time from vbclk to ctlo1 <47> t ctl1d 1.9 5.5 ns remark n = 7 to 0 remark n = 7 to 0 vbclk (input) <38> ctcsin3 (input) <39> <40> ctcsin2 (input) <41> <42> ctcsin1 (input) <43> ctcson2 (output) <44> <44> <45> ct502in0 (input) <46> ctlo1 (output) <47> <47> chapter 11 nu85e500 250 design manual a13195ej5v0dm (12) vsb timing parameter symbol conditions min. max. unit vba setup time (to vbclk ) ? t vbas1 when using page rom 1.5 ns vba hold time (from vbclk ) ? t vbah1 when using page rom 1.2 ns vdcsz setup time (to vbclk ) ? t cszs1 1.4 ns vdcsz hold time (from vbclk ) ? t cszh1 1.0 ns vbwrite setup time (to vbclk ) ? t vbwrs1 0ns vbwrite hold time (from vbclk ) ? t vbwrh1 1.7 ns vbbenz setup time (to vbclk ) ? t benzs1 0ns vbbenz hold time (from vbclk ) ? t benzh1 2.0 ns vbctyp setup time (to vbclk ) ? t ctyps1 0ns vbctyp hold time (from vbclk ) ? t ctyph1 1.3 ns vbseq setup time (to vbclk ) ? t seqs1 0ns vbseq hold time (from vbclk ) ? t seqh1 1.3 ns vbstz setup time (to vbclk ) ? t stzs1 0ns vbstz hold time (from vbclk ) ? t stzh1 1.5 ns 251 design manual a13195ej5v0dm [memo] chapter 11 nu85e500 252 design manual a13195ej5v0dm (13) npb timing (1/2) parameter symbol conditions min. max. unit vpa address setup time (to vpstb ) <48> t vpas 20 ns vpa address hold time (from vpstb ) <49> t vpah 20 ns vpwrite setup time (to vpstb ) <50> t vpwrs 20 ns vpwrite hold time (from vpstb ) <51> t vpwrh 20 ns vpd data setup time (to vpstb ) <52> t vpds 20 ns vpd data hold time (from vpstb ) <53> t vpdh 20 ns delay time from vpstb to vpd data <54> t vpdd 0.7 8.0 ns vpubenz setup time (to vpstb ) <55> t vpubs 20 ns vpubenz hold time (from vpstb ) <56> t vpubh 20 ns delay time from vpstb to ctcson4 <57> t cso4d 5ns delay time from vpstb to ctcson3 <58> t cso3d 5ns delay time from vpstb to ctcson1 <59> t cso1d 5ns delay time from vpstb to ctcson0 <60> t cso0d 5ns delay time from vpa address to ct502on1 <61> t c2o1d 5ns delay time from vpa address to ct502on0 <62> t c2o0d 5ns remark n = 7 to 0 chapter 11 nu85e500 253 design manual a13195ej5v0dm (13) npb timing (2/2) remark n = 7 to 0 vpa13 to vpa0 (input) vpd15 to vpd0 (input) vpstb (input) ctcson4 (output) <57> ctcson3 (output) <58> ctcson1 (output) <59> ctcson0 (output) <60> <61> ct502on1 (output) <62> ct502on0 (output) vpwrite (input) vpd15 to vpd0 (output) vpubenz (input) <48> <49> undefined undefined <50> <51> <52> <53> <54> <55> <56> 254 design manual a13195ej5v0dm chapter 12 nu85e502 (under development) the nu85e502 is an sdram controller for the nb85e and nb85et. the nu85e502 is used by connecting to the nu85e500 or nb85e500 according to the target cpu core. target cpu core type of connected external memory memory controller (memc) nb85e nu85e500 + nu85e502 nb85e, nb85et sdram nb85e500 + nu85e502 remark for details of the nb85e500 and nu85e500, refer to chapter 10 nb85e500 and chapter 11 nu85e500 , respectively. 12. 1 outline the nu85e502 is a macro for controlling synchronous dram (sdram). the nu85e502 can be used to start the external sdram bus cycle when it is connected to the nu85e500 (or nb85e500), and to the nb85e (or nb85et) via the vsb. the nu85e502 is used connected to the nu85e500 (or nb85e500). up to eight nu85e502 can be connected. chapter 12 nu85e502 255 design manual a13195ej5v0dm 12. 1. 1 symbol diagram number of grids 22.3k grids 41.6k grids (including wiring area) number of separation simulation patterns 20.3k out in out out out out out in in in in out in out in in in/out out out out in in in in in out in in a (25:0) d (31:0) sdrasz sdcasz sdwez cke dqm (3:0) vptclk in vpwrite vpresz ct502i (1:0) ct502o (1:0) vbwrite vbwait vbahld ctlo1 vblast vpd (15:0) ctcsi (3:0) ctcso (4:0) vpstb ctlo0 vbd (31:0) vdcsz vbbenz (3:0) vba (25:0) vbclk vbseq (2:0) mten in hldakz chapter 12 nu85e502 256 design manual a13195ej5v0dm 12. 1. 2 pin capacitance remark c in : capacitance of only input pin c inewl : value of c in with wiring capacitance (estimated wire length capacitance) taken into consideration (l = 10 mm) (1) input pins (1/2) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) vbclk 0.021 1.921 vbseq0 0.013 1.913 vba25 0.060 1.960 vbwrite 0.057 1.957 vba24 0.064 1.964 vpstb 0.012 1.912 vba23 0.095 1.995 vpwrite 0.015 1.915 vba22 0.061 1.961 ctcso4 0.049 1.949 vba21 0.062 1.962 ctcso3 0.051 1.951 vba20 0.060 1.960 ctcso2 0.013 1.913 vba19 0.061 1.961 ctcso1 0.021 1.921 vba18 0.101 2.001 ctcso0 0.008 1.908 vba17 0.100 2.000 ct502o1 0.019 1.919 vba16 0.068 1.968 ct502o0 0.030 1.930 vba15 0.092 1.992 ctlo1 0.066 1.966 vba14 0.114 2.014 ctlo0 0.019 1.919 vba13 0.080 1.980 mten 0.082 1.982 vba12 0.092 1.992 hldakz 0.097 1.997 vba11 0.093 1.993 d31 0.057 1.957 vba10 0.094 1.994 d30 0.076 1.976 vba9 0.061 1.961 d29 0.085 1.985 vba8 0.062 1.962 d28 0.089 1.989 vba7 0.068 1.968 d27 0.114 2.014 vba6 0.061 1.961 d26 0.109 2.009 vba5 0.061 1.961 d25 0.090 1.990 vba4 0.099 1.999 d24 0.068 1.968 vba3 0.094 1.994 d23 0.066 1.966 vba2 0.092 1.992 d22 0.095 1.995 vba1 0.061 1.961 d21 0.089 1.989 vba0 0.093 1.993 d20 0.066 1.966 vdcsz 0.024 1.924 d19 0.060 1.960 vbbenz3 0.008 1.908 d18 0.093 1.993 vbbenz2 0.008 1.908 d17 0.062 1.962 vbbenz1 0.008 1.908 d16 0.062 1.962 vbbenz0 0.036 1.936 d15 0.064 1.964 vpresz 0.011 1.911 d14 0.068 1.968 vbseq2 0.008 1.908 d13 0.061 1.961 vbseq1 0.013 1.913 d12 0.087 1.987 chapter 12 nu85e502 257 design manual a13195ej5v0dm (1) input pins (2/2) pin name c in (pf) c inewl (pf) pin name c in (pf) c inewl (pf) d11 0.028 1.928 d4 0.056 1.956 d10 0.073 1.973 d3 0.102 2.002 d9 0.033 1.933 d2 0.058 1.958 d8 0.060 1.960 d1 0.056 1.956 d7 0.067 1.967 d0 0.078 1.978 d6 0.048 1.948 vptclk 0.061 1.961 d5 0.060 1.960 (2) output pins pin name c max (pf) pin name c max (pf) pin name c max (pf) vbd31 6.566 vbd6 6.558 a16 12.976 vbd30 6.579 vbd5 6.575 a15 13.069 vbd29 6.572 vbd4 6.578 a14 13.067 vbd28 6.562 vbd3 6.576 a13 13.001 vbd27 6.579 vbd2 6.570 a12 13.276 vbd26 6.563 vbd1 6.569 a11 13.245 vbd25 6.576 vbd0 6.578 a10 13.016 vbd24 6.575 vbwait 6.560 a9 13.006 vbd23 6.580 vbahld 6.493 a8 13.026 vbd22 6.571 vblast 6.580 a7 12.980 vbd21 6.579 ctcsi3 13.057 a6 13.245 vbd20 6.575 ctcsi2 13.336 a5 12.954 vbd19 6.578 ctcsi1 13.338 a4 13.265 vbd18 6.564 ctcsi0 13.236 a3 13.031 vbd17 6.575 ct502i1 13.336 a2 13.040 vbd16 6.576 ct502i0 13.338 a1 13.002 vbd15 6.571 a25 13.057 a0 13.040 vbd14 6.574 a24 12.993 sdrasz 13.058 vbd13 6.573 a23 12.989 sdcasz 13.056 vbd12 6.579 a22 12.977 sdwez 13.054 vbd11 6.571 a21 12.981 cke 13.064 vbd10 6.579 a20 12.990 dqm3 13.065 vbd9 6.574 a19 12.972 dqm2 13.070 vbd8 6.573 a18 13.070 dqm1 13.055 vbd7 6.562 a17 12.892 dqm0 13.062 chapter 12 nu85e502 258 design manual a13195ej5v0dm (3) i/o pins pin name c max (pf) c in (pf) c inewl (pf) pin name c max (pf) c in (pf) c inewl (pf) vpd15 6.565 0.069 1.969 vpd7 6.575 0.059 1.959 vpd14 6.560 0.073 1.973 vpd6 6.556 0.077 1.977 vpd13 6.573 0.061 1.961 vpd5 6.561 0.072 1.972 vpd12 6.554 0.079 1.979 vpd4 6.575 0.058 1.958 vpd11 6.585 0.049 1.949 vpd3 6.577 0.057 1.957 vpd10 6.578 0.056 1.956 vpd2 6.571 0.063 1.963 vpd9 6.560 0.073 1.973 vpd1 6.573 0.061 1.961 vpd8 6.573 0.061 1.961 vpd0 6.567 0.067 1.967 12. 2 initialization of internal registers before executing the test program, be sure to execute an instruction to assign initial values to the internal registers used in the test program execution. failure to do this will result in the propagation of undefined values. chapter 12 nu85e502 259 design manual a13195ej5v0dm 12. 3 pin functions pin name i/o function vbclk input internal system clock input vba25 to vba0 input address input vbd31 to vbd0 output data output vdcsz input chip select input vbbenz3 to vbbenz0 input byte enable input vpresz input reset input vbseq2 to vbseq0 input sequential status input vbwrite input read/write status input vbwait output wait response output vbahld output address hold response output vblast output last response output vpd15 to vpd0 i/o data i/o (for npb) vpstb input data strobe input (for npb) nb85e/nb85et connection pins vpwrite input write access strobe input (for npb) ctcsi3 to ctcsi0 output control output to nu85e500/nb85e500 ctcso4 to ctcso0 input control input from nu85e500/nb85e500 ct502i1, ct502i0 output control output to nu85e500/nb85e500 ct502o1, ct502o0 input control input from nu85e500/nb85e500 ctlo1, ctlo0 input control input from nu85e500/nb85e500 mten input test mode enable input from nu85e500/nb85e500 nu85e500/nb85e500 connection pins hldakz input bus hold status input from nu85e500/nb85e500 a25 to a0 output external memory address output d31 to d0 input external memory data input sdrasz output sdram row address strobe output sdcasz output sdram column address strobe output sdwez output sdram data write enable output cke output clock enable output external memory connection pins dqm3 to dqm0 output data mask output test mode pins vptclk input test clock input chapter 12 nu85e502 260 design manual a13195ej5v0dm 12. 4 electrical specifications (preliminary) the following specifications are for a single macro. an actual chip consists of two or more macros. design the system so that all the specifications of the individual macros are satisfied when the chip is used. 12. 4. 1 absolute maximum ratings parameter symbol ratings unit supply voltage v dd ? 0.5 to +4.6 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 12. 4. 2 recommended operation range parameter symbol min. typ. max. unit supply voltage v dd 3.0 3.3 3.6 v operating ambient temperature t a ? 40 +85 c clock cycle t cyk 15.0 ns 12. 4. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode 0.11 0.17 ma/mhz supply current i dd2 in stop mode 0 1.0 a remarks 1. the above supply current value is a reference value calculated from the number of grids. 2. the typ. value is a reference value for when t a = 25 c, v dd = 3.3 v. 261 design manual a13195ej5v0dm [memo] chapter 12 nu85e502 262 design manual a13195ej5v0dm 12. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) (1) sdram read timing (1/2) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time 1 from vbclk to row address <2> t sdrad1 during bank precharge command 2.7 9.5 ns delay time 2 from vbclk to row address <3> t sdrad2 during bank active command 2.7 9.5 ns delay time from vbclk to column address <4> t sdcad 2.2 8.6 ns delay time from vbclk to sdrasz <5> t srd 2.3 6.9 ns delay time from vbclk to sdcasz <6> t scd 2.4 7.1 ns delay time from vbclk to sdwez <7> t swd 2.3 6.9 ns delay time from vbclk to dqm <8> t dqd 2.3 7.1 ns data setup time (to vbclk )<9>t ds2 0ns data hold time (from vbclk ) <10> t dh2 0.8 ns delay time from vbclk to vbd <11> t vbd3 5.5 ns delay time from vbclk to vbd <12> t vbd4 1.5 ns delay time from vbclk to vbwait, vbahld, vblast <13> t vrd3 5.0 ns delay time from vbclk to vbwait, vbahld, vblast <14> t vrd4 1.4 ns delay time from vbclk to cke <15> t cked 2.2 6.6 ns chapter 12 nu85e502 263 design manual a13195ej5v0dm (1) sdram read timing (2/2) note signal of the nu85e500 (or nb85e500) remarks 1. tw: wait state tprec: bank precharge command state tbcw: wait state inserted by setting the bcw1 and bcw0 bits of the sdram configuration register n (scrn) (n = 7 to 0) tact: bank active command state tread: read command state tlate: wait state of latency portion 2. the level of the broken line portion of the d31 to d0 signals is undefined. the level of the broken line portion of the vbd31 to vbd0, vbwait, vbahld, and vblast signals indicates undefined state (weak unknown) in which the bus holder in the nb85e (or nb85et) is driving. <2> a25 to a0 (output) tprec csz7 to csz0 (output) note sdcasz (output) d31 to d0 (input) cke (output) <1> tbcw tact tbcw tread tread <3> <4> sdrasz (output) <5> sdwez (output) <6> <10> <9> tlate vbclk (input) <15> dqm3 to dqm0 (output) <8> tlate tw <9> vbd31 to vbd0 (output) <12> <11> <11> vbwait (output) vbahld (output) vblast (output) <13> <14> <4> <5> <5> <5> <8> <15> <10> <7> <7> <6> chapter 12 nu85e502 264 design manual a13195ej5v0dm (2) sdram write timing (1/2) parameter symbol conditions min. max. unit vbclk input cycle <1> t cyk 15.0 ns delay time 1 from vbclk to row address <2> t sdrad1 during bank precharge command 2.7 9.5 ns delay time 2 from vbclk to row address <3> t sdrad2 during bank active command 2.7 9.5 ns delay time from vbclk to column address <4> t sdcad 2.2 8.6 ns delay time from vbclk to sdrasz <5> t srd 2.3 6.9 ns delay time from vbclk to sdcasz <6> t scd 2.4 7.1 ns delay time from vbclk to sdwez <7> t swd 2.3 6.9 ns delay time from vbclk to dqm <8> t dqd 2.3 7.1 ns delay time from vbclk to vbwait, vbahld, vblast <13> t vrd3 5.0 ns delay time from vbclk to vbwait, vbahld, vblast <14> t vrd4 1.4 ns delay time from vbclk to cke <15> t cked 2.2 6.6 ns chapter 12 nu85e502 265 design manual a13195ej5v0dm (2) sdram write timing (2/2) note signal of the nu85e500 remarks 1. tw: wait state tprec: bank precharge command state tbcw: wait state inserted by setting the bcw1 and bcw0 bits of the sdram configuration register n (scrn) (n = 7 to 0) tact: bank active command state twr: write command state twpre: state indicating a precharge twe: state indicating the end of a write cycle 2. the level of the broken line portion of the vbd31 to vbd0, vbwait, vbahld, and vblast signals indicates undefined state (weak unknown) in which the bus holder in the nb85e is driving. the level of the broken line portion of the do31 to do0 signals is undefined. <2> a25 to a0 (output) tprec csz7 to csz0 (output) sdcasz (output) cke (output) <1> tbcw tact tbcw twr twr sdrasz (output) sdwez (output) <6> twpre vbclk (input) dqm3 to dqm0 (output) twe tw do31 to do0 (output) vbd31 to vbd0 (input) vbwait (output) vbahld (output) vblast (output) <3> <4> <4> <5> <5> <5> <5> <7> <8> <7> <7> <8> <6> <7> <8> <15> <13> <14> <15> note note note chapter 12 nu85e502 266 design manual a13195ej5v0dm (3) nu85e500/nb85e500 connection signal timing parameter symbol conditions min. max. unit delay time from vbclk to ct502i1 <16> t c2i1d 1.4 4.0 ns delay time from vbclk to ct502i0 <17> t c2i0d 1.8 5.5 ns ctlo1 setup time (to vbclk ) <18> t ctl1s 1.3 ns ctlo1 hold time (from vbclk ) <19> t ctl1h 1.0 ns delay time from vbclk to ctcsi3 <20> t csi3d 1.8 5.2 ns delay time from vbclk to ctcsi2 <21> t csi2d 1.8 5.3 ns delay time from vbclk to ctcsi1 <22> t csi1d 1.5 4.2 ns ctcso2 setup time (to vbclk ) <23> t cso2s 1.9 ns ctcso2 hold time (from vbclk ) <24> t cso2h 0.5 ns hldakz setup time (to vbclk ) <25> t haks 0ns hldakz hold time (from vbclk ) <26> t hakh 0.8 ns vbclk (input) ct502i1 (output) <17> <17> ct502i0 (output) ctlo1 (input) <18> <19> <16> <16> ctcsi2 (output) <22> <22> ctcsi1 (output) ctcso2 (input) <23> <24> <21> <21> ctcsi3 (output) <20> <20> hldakz (output) <25> <26> chapter 12 nu85e502 267 design manual a13195ej5v0dm (4) vsb timing parameter symbol conditions min. max. unit vba setup time (to vbclk ) ? t vbas2 7.9 ns vba hold time (from vbclk ) ? t vbah2 0.3 ns vdcsz setup time (to vbclk ) ? t cszs2 3.7 ns vdcsz hold time (from vbclk ) ? t cszh2 0.1 ns vbwrite setup time (to vbclk ) ? t vbwrs2 0ns vbwrite hold time (from vbclk ) ? t vbwrh2 1.6 ns vbbenz setup time (to vbclk ) ? t benzs2 0ns vbbenz hold time (from vbclk ) ? t benzh2 1.0 ns vbseq setup time (to vbclk ) ? t seqs2 5.2 ns vbseq hold time (from vbclk ) ? t seqh2 0.5 ns 268 design manual a13195ej5v0dm appendix revision history revisions up to the previous edition are shown below. the ?pages? column indicates pages in the older documents. (1) 1st edition 2nd edition pages description p.16 modification of the explanation in 1. 2. 4 initialize pp.18 to 20 modification of the number of grids in 2. 1. 1 symbol diagram pp.21 to 23 modification of 2. 1. 2 pin capacitance p.26 modification of 2. 3. 3 dc characteristics p.26 addition of cpu operating frequency in 2. 3. 4 ac characteristics p.31 addition of caution in 2. 3. 4 (6) (e) i 2 c bus mode p.32 addition of figure 2-1. example of circuit construction of serial interface (iic0) input/output pin p.35 modification of 2. 4 (6) write timing 1 p.35 modification of 2. 4 (7) write timing 2 p.38 modification of 2. 4 (12) external wait input write timing 1 p.38 modification of 2. 4 (13) external wait input write timing 2 p.40 modification of 2. 4 (17) (a) 3-wire serial i/o mode p.43 modification of 3. 1 outline p.44 modification of the number of separation simulation patterns in 3. 1. 1 symbol diagram pp.46, 47 modification of 3. 1. 2 pin capacitance p.48 modification of 3. 2 resetb signal pp.51 to 62 modification of 3. 5 electrical specifications p.63 modification of 4. 1 outline p.64 modification of the number of separation simulation patterns in 4. 1. 1 symbol diagram pp.66 to 68 modification of 4. 1. 2 pin capacitance p.69 modification of 4. 2 resetb signal pp.72 to 87 modification of 4. 5 electrical specifications pp.89 to 107 addition of chapter 5 v30mx pp.109 to 119 addition of chapter 6 V30MZ appendix revision history 269 design manual a13195ej5v0dm (2) 2nd edition 3rd edition pages description p.17 change of ?under development? for the 78k/0 core to ?developed? in chapter 2 78k/0 core. deletion of flash memory versions (nak0hf4 and nak0hf8) p.25 deletion of description ?preliminary? from 2.3 electrical specifications p.41 deletion of a flash memory version (na851fxx) p.42 modification of the number of grids (including wiring area) in 3.1.1 symbol diagram p.50 deletion of description ?external capacitance load of internal ram data output pin? from (1) how to calculate the current consumption value of the v851 core in 3.5.3 dc characteristics p.61 deletion of a flash memory version (na853fxx) p.62 modification of the number of grids in 4.1.1 symbol diagram p.71 deletion of description ?external capacitance load of internal ram data output pin? from (1) how to calculate the current consumption value of the v853 core in 4.5.3 dc characteristics pp.119 through 154 addition of chapter 7 nb85e pp.155 through 204 addition of chapter 8 nb85e50x pp. 139, 140, 142, 148, 149, 151, 152, 153 modification of the hold time in 7.4.4 ac characteristics pp.155 through 204 change of name of sdram controller from ?nb85e502? to ?nu85e502? pp. 194, 195, 198, 204 addition of description regarding hldakz pin appendix revision history 270 design manual a13195ej5v0dm (3) 3rd edition 4th edition pages description throughout ? deletion of description regarding dram controller (nb85e501) ? modification of name of sdram controller from ?nb85e502? to ?nu85e502? pp.20, 21 correction of the number of grids of nak0hm0, nak0hm4, and nak0hm8 p.44 correction of the number of grids of v851 core p.64 correction of the number of grids of v853 core p.90 correction of the number of grids of v30mx p.93 correction of 5. 3. 2 reset signal p.108 correction of the number of grids of V30MZ p.110 correction of 6. 3. 1 reset signal p.120 correction of the number of grids and the number of separation simulation patterns of nb85e pp.135, 136 correction of 7. 3 pin functions pp.138 to 142, 144 to 149, 151 to 153 correction of 7. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) pp.155 to 159 addition of chapter 8 nb85e901 pp.161 to 199 addition of chapter 9 nb85et p.201 correction of the number of grids and the number of separation simulation patterns of nb85e500 p.211 correction of 10. 3 pin functions p.212 correction of 10. 4. 3 dc characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) pp.214 to 233 correction of 10. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) pp.235 to 267 addition of chapter 11 nu85e500 p.270 correction of the number of grids and the number of separation simulation patterns of nu85e502 pp.270, 271, 274 addition of description regarding hldakz pin pp.276 to 281 correction of 12. 4. 4 ac characteristics (t a = ? ? ? ? 40 to +85 c, v dd = 3.3 v 0.3 v) although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: +82-2-528-4411 taiwan nec electronics taiwan ltd. fax: +886-2-2719-5951 address north america nec electronics inc. corporate communications dept. fax: +1-800-729-9288 +1-408-588-6130 europe nec electronics (europe) gmbh market communication dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: +81- 44-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 01.11 name company from: tel. fax facsimile message |
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